G06F7/501

ANALOG-TO-DIGITAL CONVERSION METHOD, ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR

An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.

Geometric synthesis

A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

Geometric synthesis

A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

Method of Performing Hardware Efficient Unbiased Rounding of a Number
20220334799 · 2022-10-20 ·

A method and hardware for performing hardware efficient unbiased rounding of a number includes receiving the number in a binary format having a first portion and a second portion. The first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point. The method includes adding a first amount to the number to obtain a first value. Further the method comprises determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit. The controlling value is either the received number in the binary format or the first value. The method further includes adding a second amount to ‘b+1’ LSBs of the first value to obtain a second value if the bit above the rounding point for the controlling value is a ‘0’ bit and rounding the number by truncating the last b bits of the second value or the last b bits of the first value based on the determination.

Method of Performing Hardware Efficient Unbiased Rounding of a Number
20220334799 · 2022-10-20 ·

A method and hardware for performing hardware efficient unbiased rounding of a number includes receiving the number in a binary format having a first portion and a second portion. The first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point. The method includes adding a first amount to the number to obtain a first value. Further the method comprises determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit. The controlling value is either the received number in the binary format or the first value. The method further includes adding a second amount to ‘b+1’ LSBs of the first value to obtain a second value if the bit above the rounding point for the controlling value is a ‘0’ bit and rounding the number by truncating the last b bits of the second value or the last b bits of the first value based on the determination.

ARITHMETIC UNIT FOR APPROXIMATE CALCULATIONS IN NEURAL NETWORKS

An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers. The arithmetic unit includes arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, and the arithmetic modules being connected in an adder that is designed to calculate digits of the product or of the sum from the individual products or from the individual sums. An arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for the running time of the arithmetic unit.

ARITHMETIC UNIT FOR APPROXIMATE CALCULATIONS IN NEURAL NETWORKS

An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers. The arithmetic unit includes arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, and the arithmetic modules being connected in an adder that is designed to calculate digits of the product or of the sum from the individual products or from the individual sums. An arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for the running time of the arithmetic unit.

Matrix Multiply Accelerator For Variable Bitwidth Operands

A system and method for multiplying first and second matrices are provided. For the first matrix, a number of bit slice vectors for each row are generated based on the bit resolution, and a first bit slice tensor is generated based on the bit slice vectors for each row. For the second matrix, a number of bit slice vectors for each column are generated based on the bit resolution, and a second bit slice tensor is generated based on the bit slice vectors for each row. The first and second bit slice tensors are multiplied by a matrix multiply accelerator (MMA) to generate an output matrix.

Matrix Multiply Accelerator For Variable Bitwidth Operands

A system and method for multiplying first and second matrices are provided. For the first matrix, a number of bit slice vectors for each row are generated based on the bit resolution, and a first bit slice tensor is generated based on the bit slice vectors for each row. For the second matrix, a number of bit slice vectors for each column are generated based on the bit resolution, and a second bit slice tensor is generated based on the bit slice vectors for each row. The first and second bit slice tensors are multiplied by a matrix multiply accelerator (MMA) to generate an output matrix.

Mitigating Atmospheric Effects From Geographical Anomalies on Reference Pressure Estimates

A method involves determining an estimated position of a mobile device within a region. Atmospheric data measurement stations are identified within the region. A geographical anomaly is identified within the region that physically intervenes between the mobile device and a first atmospheric data measurement station. Based on a positional relationship between the mobile device, the geographical anomaly, and the first atmospheric data measurement station, it is determined that atmospheric pressure measurements collected at the first atmospheric data measurement station should be conditionally used for determining a reference pressure estimate. The reference pressure estimate is determined using a plurality of atmospheric pressure measurements collected at the atmospheric data measurement stations and conditionally using the atmospheric pressure measurements collected at the first atmospheric data measurement station. An estimated altitude of the mobile device is determined using a measurement of atmospheric pressure at the mobile device and the reference pressure estimate.