A method involves determining an estimated position of a mobile device within a region. Atmospheric data measurement stations are identified within the region. A geographical anomaly is identified within the region that physically intervenes between the mobile device and a first atmospheric data measurement station. Based on a positional relationship between the mobile device, the geographical anomaly, and the first atmospheric data measurement station, it is determined that atmospheric pressure measurements collected at the first atmospheric data measurement station should be conditionally used for determining a reference pressure estimate. The reference pressure estimate is determined using a plurality of atmospheric pressure measurements collected at the atmospheric data measurement stations and conditionally using the atmospheric pressure measurements collected at the first atmospheric data measurement station. An estimated altitude of the mobile device is determined using a measurement of atmospheric pressure at the mobile device and the reference pressure estimate.

A combined adder for N logical bits to produce a sum from a first addend having N first addend bits and a second addend having N second addend bits. A least significant adder produces a segment sum of the least significant bits and a carry out. Segment adder pairs are used for each higher order of significant sums. One segment adder produces a segment sum portion, and the other produces an incremented segment sum portion. Carry logic associated with each segment is utilized with a multiplexer to select the incremented segment sum portion or the segment sum portion. The selected segment sum portions are assembled with a most significant carry out to produce the sum.

A combined adder for N logical bits to produce a sum from a first addend having N first addend bits and a second addend having N second addend bits. A least significant adder produces a segment sum of the least significant bits and a carry out. Segment adder pairs are used for each higher order of significant sums. One segment adder produces a segment sum portion, and the other produces an incremented segment sum portion. Carry logic associated with each segment is utilized with a multiplexer to select the incremented segment sum portion or the segment sum portion. The selected segment sum portions are assembled with a most significant carry out to produce the sum.

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.

An integrated circuit is provided that includes via-configured structured logic circuitry and an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function. The embedded arithmetic block includes at least one monolithic arithmetic circuit that can perform the arithmetic function more efficiently or taking up less die space than a comparable circuit formed from the via-configured structured logic circuitry.

A fixed binary adder adds an “N”-bit second operand to a first operand having an “N”-bit fixed value (N=2.sup.M, M is a natural number) to generate “N+1”-bit output data. The fixed binary adder includes a plurality of transfer logic stages each configured with at least one logic gate, and a summation addition logic configured to generate the “N+1”-bit output data by using the “N”-bit second operand and transfer data that is generated through the plurality of transfer logic stages. The logic gate is configured with one of an AND gate, an OR gate, and a buffer gate.

A fixed binary adder adds an “N”-bit second operand to a first operand having an “N”-bit fixed value (N=2.sup.M, M is a natural number) to generate “N+1”-bit output data. The fixed binary adder includes a plurality of transfer logic stages each configured with at least one logic gate, and a summation addition logic configured to generate the “N+1”-bit output data by using the “N”-bit second operand and transfer data that is generated through the plurality of transfer logic stages. The logic gate is configured with one of an AND gate, an OR gate, and a buffer gate.

One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with generation of the sum by an adder; and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum.