The present disclosure concerns a method of executing a SoftMax function, the method comprising: (i) pre-storing in memory M fraction components (fc.sub.j) in binary form, derived from the expression 2.sup.(j/M), said fc.sub.j forming a lookup table (T) of size M; (ii) calculating, for each z.sub.i, an element y.sub.i of a number of the form 2.sup.y.sup.i; (iii) separating y.sub.i into an integral part (int.sub.i) and a fractional part (fract.sub.i); (iv) determining a lookup index (ind.sub.i) that corresponds to fract.sub.i scaled by the size M; (v) retrieving a fraction component fc.sub.i from T with ind.sub.i; (vi) generating, in a result register, a binary number representative of the exponential value of said z.sub.i, by combining said fc.sub.i retrieved from T and said int.sub.i; (v) adding the K result registers corresponding to z.sub.i into a sum register R7; and (vi) determining the K probability values p.sub.i from the K result registers and the sum register.

A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

A Bias Unit Element (UE) has a digital input and sign input, and comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

An architecture for a chopper stabilized multiplier-accumulator (MAC) uses a chop clock and common Unit Element (UE), the MAC formed as a plurality of MAC UEs receiving X and W values and a sign bit exclusive ORed with the chop clock, a plurality of Bias UEs receiving E value and a sign bit exclusive ORed with the chop clock, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

A Gain Balanced Analog Multiply-Accumulator (AMAC) has an inference memory which outputs subsets of inference data comprising X input values and one or more associated W coefficient values. The Gain Balanced AMAC has a number of Analog Multiplier-Accumulator Unit Elements (AMAC UE) in equal number to the number of X input values in each subset of inference data. In each of a series of multiply-accumulate cycles, the X input values and one or more W coefficient values from the inference memory are applied to each AMAC UE to generate a charge corresponding to the multiplication of X input value and W coefficient value of each AMAC UE which is transferred to a shared analog charge bus. The inference memory applies the X input value and W coefficient values of each subset to a different AMAC UE on subsequent cycles to balance the gain of the AMAC such that gain differences from one AMAC UE to another are not cumulative.

A method for providing transmit symbols to be transmitted by a transmitter to one or more receivers of a wireless MIMO communication system is described. The method includes receiving data to be transmitted to the one or more receivers, and obtaining the transmit symbols to be transmitted by multiplying a data vector including the data to be transmitted by a matrix, like a precoding matrix. The matrix is approximated by a plurality of matrices whose elements are positive or negative integer powers of two so that multiplying the data vector by the matrix includes a series of sub-multiplications, each of the sub-multiplications being realized only by bit shifts and additions.

A method for providing transmit symbols to be transmitted by a transmitter to one or more receivers of a wireless MIMO communication system is described. The method includes receiving data to be transmitted to the one or more receivers, and obtaining the transmit symbols to be transmitted by multiplying a data vector including the data to be transmitted by a matrix, like a precoding matrix. The matrix is approximated by a plurality of matrices whose elements are positive or negative integer powers of two so that multiplying the data vector by the matrix includes a series of sub-multiplications, each of the sub-multiplications being realized only by bit shifts and additions.

The present invention discloses a memristor array, comprising metal wires and memristors; the metal wires are arranged laterally and vertically; a memristor is arranged at the intersection of every two metal wires; the connection/disconnection of the metal wires is judged according to the resistance values of the memristors; and an adder is constituted according to the resistance value states of the memristors. The present invention provides a memristor-CMOS hybrid multiplication core circuit, in which one input of multiplication can be stored in a memristor network, one part of operation is completed in a memory network, the other part of operation is completed through a CMOS circuit, thereby reducing frequent data calls by half, and the power consumption of the CMOS circuit is further reduced by reducing competitive adventure in the operation process, thereby greatly reducing the overall energy consumption.