A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

To reduce the reliance on software for complex computations used in machine sensory perception, a sensory perception accelerator may include a neural network accelerator a linear algebra accelerator. The neural network accelerator may include systolic arrays to perform neural network computation circuits concurrently on image data and audio data. The linear algebra accelerator may include matrix computation circuits operable to perform matrix operations on image data and motion data.

To reduce the reliance on software for complex computations used in machine sensory perception, a sensory perception accelerator may include a neural network accelerator a linear algebra accelerator. The neural network accelerator may include systolic arrays to perform neural network computation circuits concurrently on image data and audio data. The linear algebra accelerator may include matrix computation circuits operable to perform matrix operations on image data and motion data.

Disclosed are a method and an apparatus for performing convolution operation on folded feature data. The method comprises: reading the folded feature data provided to a convolution layer and an original convolution kernel from a dynamic random access memory (DRAM); pre-processing the folded feature data and the original convolution kernel; storing the pre-processed folded feature data into a static random-access memory (SRAM); folding the pre-processed original convolution kernel in at least one dimension of width or height according to a folding manner of the folded feature data to generate one or more folded convolution kernels corresponding to the original convolution kernel; storing the one or more folded convolution kernels in the SRAM; and reading the pre-processed folded feature data and the one or more folded convolution kernels from the SRAM into a calculation unit for convolving the pre-processed folded feature data with the one or more folded convolution kernels.

Disclosed are a method and an apparatus for performing convolution operation on folded feature data. The method comprises: reading the folded feature data provided to a convolution layer and an original convolution kernel from a dynamic random access memory (DRAM); pre-processing the folded feature data and the original convolution kernel; storing the pre-processed folded feature data into a static random-access memory (SRAM); folding the pre-processed original convolution kernel in at least one dimension of width or height according to a folding manner of the folded feature data to generate one or more folded convolution kernels corresponding to the original convolution kernel; storing the one or more folded convolution kernels in the SRAM; and reading the pre-processed folded feature data and the one or more folded convolution kernels from the SRAM into a calculation unit for convolving the pre-processed folded feature data with the one or more folded convolution kernels.

A scalar multiplication operation includes an iterative procedure performing a set of operations at each iteration on a bit or on a group of consecutive bits of a secret key. The multiplication operation includes multiplying values of projective format coordinates by a random value. The random value is a product of a random number generated over a range having as end value a first value, with a second value, which is larger than said first value. The first value is a power of two of a word size multiplied by a multiplier value, minus one. The second value is equal to a power of two of a number of bits of the coordinates divided by the first value. The multiplier value is an integer greater than or equal to one and smaller than a ratio of said number of bits to the word size.

A scalar multiplication operation includes an iterative procedure performing a set of operations at each iteration on a bit or on a group of consecutive bits of a secret key. The multiplication operation includes multiplying values of projective format coordinates by a random value. The random value is a product of a random number generated over a range having as end value a first value, with a second value, which is larger than said first value. The first value is a power of two of a word size multiplied by a multiplier value, minus one. The second value is equal to a power of two of a number of bits of the coordinates divided by the first value. The multiplier value is an integer greater than or equal to one and smaller than a ratio of said number of bits to the word size.

A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.

A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.