A first multiplex circuit generates a first multiplex signal obtained by time-divisionally multiplexing a first real part and a first imaginary part of a first complex number. A second multiplex circuit generates a second multiplex signal obtained by time-divisionally multiplexing a second real part and a second imaginary part of a second complex number. A multiply-subtract operation circuit performs a multiply-subtract operation of the first and second multiplex signals. A third multiplex circuit generates a third multiplex signal obtained by time-divisionally multiplexing the first and second real parts. A fourth multiplex circuit generates a fourth multiplex signal obtained by time-divisionally multiplexing the first and second imaginary parts. A multiply-accumulate operation circuit performs a multiply-accumulate operation of the third and fourth multiplex signals. A fifth multiplex circuit generates a fifth multiplex signal obtained by time-divisionally multiplexing output values of the multiply-subtract operation circuit and the multiply-accumulate operation circuit.

A first multiplex circuit generates a first multiplex signal obtained by time-divisionally multiplexing a first real part and a first imaginary part of a first complex number. A second multiplex circuit generates a second multiplex signal obtained by time-divisionally multiplexing a second real part and a second imaginary part of a second complex number. A multiply-subtract operation circuit performs a multiply-subtract operation of the first and second multiplex signals. A third multiplex circuit generates a third multiplex signal obtained by time-divisionally multiplexing the first and second real parts. A fourth multiplex circuit generates a fourth multiplex signal obtained by time-divisionally multiplexing the first and second imaginary parts. A multiply-accumulate operation circuit performs a multiply-accumulate operation of the third and fourth multiplex signals. A fifth multiplex circuit generates a fifth multiplex signal obtained by time-divisionally multiplexing output values of the multiply-subtract operation circuit and the multiply-accumulate operation circuit.

A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.

A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

A gaze point calculation apparatus includes: a first cache register, a multiplexer, an arithmetic unit assembly, and a state machine. The first cache register is configured to receive and store first coordinates and a plurality of calibration parameters required when second required are obtained through calculation according to the first coordinates. The state machine is configured to control the multiplexer to select each time at least one value from the first cache register and transmit same to the arithmetic unit assembly. The arithmetic unit assembly is configured to perform a preset operation on the at least one value received each time until the second coordinates are obtained, and output the second coordinates under control of the state machine.

A gaze point calculation apparatus includes: a first cache register, a multiplexer, an arithmetic unit assembly, and a state machine. The first cache register is configured to receive and store first coordinates and a plurality of calibration parameters required when second required are obtained through calculation according to the first coordinates. The state machine is configured to control the multiplexer to select each time at least one value from the first cache register and transmit same to the arithmetic unit assembly. The arithmetic unit assembly is configured to perform a preset operation on the at least one value received each time until the second coordinates are obtained, and output the second coordinates under control of the state machine.

The present invention relates to convolution neural networks (CNN) and methods for improving computational efficiency of multiply accumulate (MAC) array structure Specifically, the invention relates to cutting of activation data into a number of tiles for increasing overall computation efficiency. The invention discloses techniques to cut an activation data into a plurality of tiles by using a 3-D convolution computation core and support bigger tensor sizes. Lastly, the invention provides adaptive scheduling of MAC array to achieve high utilization in multi-precision neural network acceleration.

The present invention relates to convolution neural networks (CNN) and methods for improving computational efficiency of multiply accumulate (MAC) array structure Specifically, the invention relates to cutting of activation data into a number of tiles for increasing overall computation efficiency. The invention discloses techniques to cut an activation data into a plurality of tiles by using a 3-D convolution computation core and support bigger tensor sizes. Lastly, the invention provides adaptive scheduling of MAC array to achieve high utilization in multi-precision neural network acceleration.