Aspects of the disclosure provide methods and apparatuses for point cloud compression and decompression. In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. The processing circuitry determines to use a prediction mode for coding (encoding/decoding) information associated with a current point in a point cloud. In the prediction mode, the information associated with the current point is predicted based on one or more neighbor points of the current point. The processing circuitry calculates, using integer operations, a distance-based weighted average value based on distances of the one or more neighbor points to the current point, and determines the information associated with the current point based on the distance-based weighted average value.

An exponential calculator based on parallel computing is disclosed. The exponential calculator includes a master system and a plurality of nodes interconnected with each other to transfer and receive information and perform sub-computations independently and simultaneously. The master system is configured to select a number of nodes from the plurality of nodes required to perform sub-computations for calculation of an integer exponent. The selected nodes is configured to receive value of a node base and a node exponent from the master system. The selected nodes calculate a first computation value, a second computation value and a third computation value. The master system is further configured to instruct a sub-set of the selected nodes to perform summation of a final sub-computation of the selected nodes and provide an output.

An exponential calculator based on parallel computing is disclosed. The exponential calculator includes a master system and a plurality of nodes interconnected with each other to transfer and receive information and perform sub-computations independently and simultaneously. The master system is configured to select a number of nodes from the plurality of nodes required to perform sub-computations for calculation of an integer exponent. The selected nodes is configured to receive value of a node base and a node exponent from the master system. The selected nodes calculate a first computation value, a second computation value and a third computation value. The master system is further configured to instruct a sub-set of the selected nodes to perform summation of a final sub-computation of the selected nodes and provide an output.

The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations. Multiple-cycles of a radix-m division operation may be performed to generate one or more signal states representative of a result value based at least in part on a dividend value and a divisor value.

The present disclosure relates generally to arithmetic units of processors, and may relate more particularly to multi-cycle division operations. Multiple-cycles of a radix-m division operation may be performed to generate one or more signal states representative of a result value based at least in part on a dividend value and a divisor value.

Systems and methods include reception of data including a plurality of continuous features and a first discrete feature, each of the plurality of continuous features associated with a plurality of values and the first discrete feature associated with a plurality of discrete values, determination of an overall output value of a function based on the plurality of values associated with each of the plurality of continuous features, determination, for each discrete value of the plurality of discrete values, of an output value of the function based on ones of the plurality of values associated with the discrete value, scaling of the output value determined for each discrete value based on the determined output values and the overall output value, and presentation of the scaled output values.

A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2.sup.m−1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation:

[00001]$.Math.\frac{2^{i}x}{q}.Math.$ where i is the minimum positive value which satisfies:

[00002]$\frac{2^i}{\left(2^i\mathrm{mod}a\right)}>a*\left(2^m-1\right)+1q=.Math.\frac{2^i}{a}.Math.$ and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation a*x.

A fixed logic circuit configured to determine one or more of the most significant bits of the multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2.sup.m−1, and m is a positive integer, the fixed logic circuit comprising: division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation:

[00001]$.Math.\frac{2^{i}x}{q}.Math.$ where i is the minimum positive value which satisfies:

[00002]$\frac{2^i}{\left(2^i\mathrm{mod}a\right)}>a*\left(2^m-1\right)+1q=.Math.\frac{2^i}{a}.Math.$ and output logic configured to provide the one or more most significant bits of the result of the division operation as the respective one or more most significant bits of the multiplication operation a*x.

A fixed logic circuit configured to perform a multiplication operation a*x, where a is an integer constant, x is an integer variable in the range 0 to 2.sup.m−1, and m is a positive integer. The fixed logic circuit includes division logic configured to determine a predetermined number of one or more most significant bits of the result of the division operation:

└2.sup.ix/q┘

where q,i are selected such that:

a*x=└2.sup.ix/q┘

Multiplication logic determines a predetermined number of one or more least significant bits of the result of the multiplication operation a*x; and output logic combines the predetermined number of one or more most significant bits of the result of the division operation with the predetermined number of one or more least significant bits of the result of the multiplication operation so as to provide an output for the multiplication operation a*x.

A divider includes a digit recoder that recodes upper bits of a partial remainder into sets of lower-radix multiples without carry propagate addition. Elimination of the carry propagate adder makes computation of the quotient carry free and independent of the number of bits computed per cycle, thereby enabling a higher number of bits per cycle, as well as increased clock speeds.