According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.

A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

A computation unit 11 performs, for each column of a target matrix to be standardized, a computation process to compute the average and standard deviation of the value of each component of the column. A first dividing unit 12 performs, for each column of the target matrix, a first dividing process to divide the value of each component of the column by the standard deviation computed based on the column. A second dividing unit 13 performs, for each column of the target matrix, a second dividing process to divide the average computed based on the column by the standard deviation computed based on the column. A generation unit 14 which arranges the quotients computed by a plurality of second dividing processes, in a row in the order of the columns of the target matrix from which the quotients are computed, thereby generating a row vector.

A computation unit 11 performs, for each column of a target matrix to be standardized, a computation process to compute the average and standard deviation of the value of each component of the column. A first dividing unit 12 performs, for each column of the target matrix, a first dividing process to divide the value of each component of the column by the standard deviation computed based on the column. A second dividing unit 13 performs, for each column of the target matrix, a second dividing process to divide the average computed based on the column by the standard deviation computed based on the column. A generation unit 14 which arranges the quotients computed by a plurality of second dividing processes, in a row in the order of the columns of the target matrix from which the quotients are computed, thereby generating a row vector.

In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.