Provided is a fast divider including an initial parameter setting unit and an arithmetic unit. The arithmetic unit is coupled to the initial parameter setting unit that receives a divisor and a dividend, and sets a plurality of initial parameters of a sequence according to the divisor and the dividend. The plurality of initial parameters includes an initial term, a first term and a common ratio having an absolute value smaller than 1. The arithmetic unit stores a recurrence relation of the sequence and iteratively computes a quotient using the recurrence relation according to the plurality of initial parameters. The recurrence relation indicates that a (k+1).sup.th term is equal to a product of a k.sup.th term multiplied by a sum of the common ratio and 1 subtracted by a product of a (k−1).sup.th term multiplied by the common ratio. k is an integer larger than or equal to 1.

Provided is a fast divider including an initial parameter setting unit and an arithmetic unit. The arithmetic unit is coupled to the initial parameter setting unit that receives a divisor and a dividend, and sets a plurality of initial parameters of a sequence according to the divisor and the dividend. The plurality of initial parameters includes an initial term, a first term and a common ratio having an absolute value smaller than 1. The arithmetic unit stores a recurrence relation of the sequence and iteratively computes a quotient using the recurrence relation according to the plurality of initial parameters. The recurrence relation indicates that a (k+1).sup.th term is equal to a product of a k.sup.th term multiplied by a sum of the common ratio and 1 subtracted by a product of a (k−1).sup.th term multiplied by the common ratio. k is an integer larger than or equal to 1.

A logic circuit configured to calculate a quotient Q based on a modified cross-sum of an input word CP, a digital circuit having a first input for the input word CP that is a bit-wise inverted value of a number N of M-bit digits having a radix 2.sup.M from a least significant digit to a most significant digit, the circuit configured to calculate a quotient Q, M and N being positive integer numbers larger than one, wherein the digital circuit has a second input RIN that is configured to be set to zero, or to receive a remainder value from another logic circuit, and wherein the digital circuit provides for an output word Q having N digits, each digit of radix 2.sup.M, the output word Q being a raw quotient of the bit-wise inverted value of the input word CP.

Systems, apparatuses, and methods for implementing one-sided per-kernel clipping and weight transformation for neural networks are disclosed. Various parameters of a neural network are quantized from higher-bit representations to lower-bit representations to reduce memory utilization and power consumption. To exploit the effective range of quantized representations, positively biased weights are clipped and negated before convolution. Then, the results are rescaled back after convolution. A one-sided clipping technique is used for transforming weights to exploit the quantization range effectively, with the side chosen to be clipped being the biased side. This technique uses a global strategy for clipping without requiring skilled expertise. This approach allows the system to retain as much information as possible without losing unnecessary accuracy when quantizing parameters from higher-bit representations to lower-bit representations.

Systems, apparatuses, and methods for implementing one-sided per-kernel clipping and weight transformation for neural networks are disclosed. Various parameters of a neural network are quantized from higher-bit representations to lower-bit representations to reduce memory utilization and power consumption. To exploit the effective range of quantized representations, positively biased weights are clipped and negated before convolution. Then, the results are rescaled back after convolution. A one-sided clipping technique is used for transforming weights to exploit the quantization range effectively, with the side chosen to be clipped being the biased side. This technique uses a global strategy for clipping without requiring skilled expertise. This approach allows the system to retain as much information as possible without losing unnecessary accuracy when quantizing parameters from higher-bit representations to lower-bit representations.

Techniques to create and use cluster models to predict build failures are provided. In one aspect, clusters in a set of builds may be identified. The identified clusters may be used to create a model. The model may be used to predict causes of build failures. In another aspect, a failed build may be identified. A clustering model may be retrieved. A cause of problems with the failed build may be predicted using the clustering model.

Techniques to create and use cluster models to predict build failures are provided. In one aspect, clusters in a set of builds may be identified. The identified clusters may be used to create a model. The model may be used to predict causes of build failures. In another aspect, a failed build may be identified. A clustering model may be retrieved. A cause of problems with the failed build may be predicted using the clustering model.

A secret decision tree test device configured to evaluate a division condition at each of a plurality of nodes of a decision tree when learning of the decision tree is performed by secret calculation, includes a memory; and a processor configured to execute inputting a category attribute value vector composed of specific category attribute values of items of data included in a data set for learning of the decision tree, a label value vector composed of label values of the items of the data, and a group information vector indicating grouping of the items of the data into the nodes; and calculating, using the category attribute value vector, the label value vector, and the group information vector, first to fourth frequencies, to evaluate the division condition using the first to fourth frequencies.

A secret decision tree test device configured to evaluate a division condition at each of a plurality of nodes of a decision tree when learning of the decision tree is performed by secret calculation, includes a memory; and a processor configured to execute inputting a category attribute value vector composed of specific category attribute values of items of data included in a data set for learning of the decision tree, a label value vector composed of label values of the items of the data, and a group information vector indicating grouping of the items of the data into the nodes; and calculating, using the category attribute value vector, the label value vector, and the group information vector, first to fourth frequencies, to evaluate the division condition using the first to fourth frequencies.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.