A system and an accelerator circuit including a register file comprising instruction registers to store a trigonometric calculation instruction for evaluating a trigonometric function, and data registers comprising a first data register to store a floating-point input value associated with the trigonometric calculation instruction. The accelerator circuit further includes a determination circuit to identify the trigonometric calculation function and the floating-point input value associated with the trigonometric calculation instruction and determine whether the floating-point input value is in a small value range, and an approximation circuit to responsive to determining that the floating-point input value is in the small value, receive the floating-point input value and calculate an approximation of the trigonometric function with respect to the input value.

Apparatus for evaluating a mathematical function for a received input value includes a polynomial block configured to identify a domain interval containing the received input value over which the mathematical function can be evaluated, the mathematical function over the identified interval being approximated by a polynomial function; and evaluate the polynomial function for the received input value using a set of one or more stored values representing the polynomial function over the identified interval to calculate a first evaluation of the mathematical function for the received input value; and a CORDIC block for performing a CORDIC algorithm, configured to initialise the CORDIC algorithm using the first evaluation of the mathematical function for the received input value calculated by the polynomial block; and implement the CORDIC algorithm to calculate a refined evaluation of the mathematical function for the received input value.

Flexible structured-pipelined CORDIC techniques efficiently perform various CORDIC operations and support different parameters for MIMO MEQ processing. The structured-pipelined CORDIC techniques simplify signal processing flow, unify input requirements and output delay, and simplify integration. Look-up table techniques provide quick generation of control signals, reduce design and verification efforts, and facilitate design automation. In addition, the structured-pipelined CORDIC techniques are conducive to hardware sharing and reuse. The structured-pipelined CORDIC techniques reduce integrated circuit area and power consumption.

An arithmetic processing device includes a processor that calculates a constant multiplication value by multiplying a constant value obtained by dividing a first value by a natural logarithm of 2 and a data value, separates the constant multiplication value into an integer portion and a fractional portion, calculates a fractional power value corresponding to a value of the fractional portion, calculates an integer power value corresponding to a value obtained by multiplying a value of the integer portion by a second value, calculates a power addition value by adding the fractional power value and the integer power value, calculate a power subtraction value by subtracting the integer power value from the fractional power value, and calculate a division value by dividing the power subtraction value by the power addition value as a result of an execution of an arithmetic operation of a hyperbolic tangent function with the data value.

A method of generating complex exponentiation and logarithms in hardware is described that uses half the number of bits of lookup tables as the state-of-the-art. By splitting up each of the iterations into more simplified stages or using more iterations, the amount of precomputed information that must be held by the circuitry is reduced. This allows synthesis tools to take this more succinct logical description of the algorithm and make it into efficient gate level logic for fabrication into more compact integrated circuitry.

Flexible structured-pipelined CORDIC techniques efficiently perform various CORDIC operations and support different parameters for MIMO MEQ processing. The structured-pipelined CORDIC techniques simplify signal processing flow, unify input requirements and output delay, and simplify integration. Look-up table techniques provide quick generation of control signals, reduce design and verification efforts, and facilitate design automation. In addition, the structured-pipelined CORDIC techniques are conducive to hardware sharing and reuse. The structured-pipelined CORDIC techniques reduce integrated circuit area and power consumption.

This specification discloses methods and systems for implementing a chip integrated scope (i.e., chip scope (CS)), which is a feature that allows a user to scope RF signals (internally and externally to the DUT (device under test)), by using the RF receive path (including amplifier, filter, ADC, DSP) to capture and store signal traces. In some embodiments, this specification discloses methods and systems to enhance the resolution and accuracy of these signal traces by using raw and correction data for gain/phase compensation of gain/phase impairments introduced in the Rx (receiver) path. In some embodiments, the correction data is generated from one or more of the following: simulation data, characterization data, production test data.

Various embodiments of the present technology comprise a method and apparatus for an encoder. In various embodiments, the encoder is configured to perform offset and gain correction. The encoder includes a first correction circuit to perform offset and gain correction and a second correction circuit to perform additional offset and gain correction.

Various embodiments of the present technology comprise a method and apparatus for an encoder. In various embodiments, the encoder is configured to remove impairments from the signals produced by a servo motor and compute a phase that is used to determine the rotary position of the servo motor. In various embodiments, the encoder is configured to remove a DC offset, improve amplitude mismatch, and compute a phase offset.

A microcontroller includes a processor and the hardware accelerator coupled to the processor. The microcontroller is programmed to execute a processing operation able to be parameterized by at least one parameter by delivering the at least one parameter from the processor to the hardware accelerator. The microcontroller can be part of an on-board vehicle computer.