A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by $1\text{/}\sqrt[i]{d}.$
The hardware logic comprises a plurality of multipliers and adders arranged to implement a m.sup.th-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

Digital approximate squarer (aSQR)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed aSQR methods can operate asynchronously and or synchronously. For applications where low precisions is acceptable, fewer interpolations can yield less precise square approximation, which can be computed faster and with lower power consumption. Conversely, for applications where higher precision are required, more interpolations steps can generate more precise square approximation. By utilizing the disclosed aSQR method, precision objectives of a squarer approximation function can be programmed real-time and on the fly, which enables optimizing for power consumption and speed of squaring, in addition to optimize for the approximate squarer's die size and cost.

Digital approximate squarer (aSQR)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed aSQR methods can operate asynchronously and or synchronously. For applications where low precisions is acceptable, fewer interpolations can yield less precise square approximation, which can be computed faster and with lower power consumption. Conversely, for applications where higher precision are required, more interpolations steps can generate more precise square approximation. By utilizing the disclosed aSQR method, precision objectives of a squarer approximation function can be programmed real-time and on the fly, which enables optimizing for power consumption and speed of squaring, in addition to optimize for the approximate squarer's die size and cost.

A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.

A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.

Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.

Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.

Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.

Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.