G06F7/552

Compression and homomorphic encryption in secure query and analytics
11290252 · 2022-03-29 · ·

Systems and methods for end-to-end encryption and compression are described herein. A query is encrypted at a client using a homomorphic encryption scheme. The encrypted query is sent to a server where the encrypted query is evaluated over target data to generate encrypted response without decrypting the encrypted query. The result elements of the encrypted response are grouped, co-located, and compressed, without decrypting the encrypted query or the encrypted response. The compressed encrypted response is sent to the client where it is decrypted and decompressed to obtain the results of the query without revealing the query or results to the owner of the target data, an observer, or an attacker.

Compression and homomorphic encryption in secure query and analytics
11290252 · 2022-03-29 · ·

Systems and methods for end-to-end encryption and compression are described herein. A query is encrypted at a client using a homomorphic encryption scheme. The encrypted query is sent to a server where the encrypted query is evaluated over target data to generate encrypted response without decrypting the encrypted query. The result elements of the encrypted response are grouped, co-located, and compressed, without decrypting the encrypted query or the encrypted response. The compressed encrypted response is sent to the client where it is decrypted and decompressed to obtain the results of the query without revealing the query or results to the owner of the target data, an observer, or an attacker.

Secure computation system, secure computation device, secure computation method, and program

A secure computation system calculates concealed text of a difference x−r from concealed text by using concealed text and generates concealed text and of an integer portion e and a decimal fraction portion f (0≤f<1) of the difference x−r from the concealed text; reconstructs the decimal fraction portion f from the concealed text; generates, from the decimal fraction portion f and the concealed text, concealed text of a left shift value y obtained by shifting 2.sup.f, which is 2 raised to the power f which is the decimal fraction portion f, to the left by e bit; and calculates, as concealed text, concealed text of a value 2.sup.r×y obtained by multiplying 2.sup.r, which is a power of 2, by the left shift value y from the concealed text by using the concealed text.

Secure computation system, secure computation device, secure computation method, and program

A secure computation system calculates concealed text of a difference x−r from concealed text by using concealed text and generates concealed text and of an integer portion e and a decimal fraction portion f (0≤f<1) of the difference x−r from the concealed text; reconstructs the decimal fraction portion f from the concealed text; generates, from the decimal fraction portion f and the concealed text, concealed text of a left shift value y obtained by shifting 2.sup.f, which is 2 raised to the power f which is the decimal fraction portion f, to the left by e bit; and calculates, as concealed text, concealed text of a value 2.sup.r×y obtained by multiplying 2.sup.r, which is a power of 2, by the left shift value y from the concealed text by using the concealed text.

EFFICIENT SOFTMAX COMPUTATION

Solutions improving efficiency of Softmax computation applied for efficient deep learning inference in transformers and other neural networks. The solutions utilize a reduced-precision implementation of various operations in Softmax, replacing e.sup.x with 2.sup.x to reduce instruction overhead associated with computing e.sup.x, and replacing floating point max computation with integer max computation. Further described is a scalable implementation that decomposes Softmax into UnNormalized Softmax and Normalization operations.

EFFICIENT SOFTMAX COMPUTATION

Solutions improving efficiency of Softmax computation applied for efficient deep learning inference in transformers and other neural networks. The solutions utilize a reduced-precision implementation of various operations in Softmax, replacing e.sup.x with 2.sup.x to reduce instruction overhead associated with computing e.sup.x, and replacing floating point max computation with integer max computation. Further described is a scalable implementation that decomposes Softmax into UnNormalized Softmax and Normalization operations.

Method to Estimate Surface Gloss
20220065781 · 2022-03-03 ·

As described herein, a method has been developed to estimate the gloss of a black or dark sample using a color measurement system. In such a system, when measuring a higher gloss sample, more illumination light reflected from the sample surface will be directed away from the receiving sensor, and thus less signal will be detected. Using a derived sensor-signal to surface-gloss relationship, the surface gloss of a sample can be calculated by applying the measurements of the sample to the signal to gloss relationship to obtain a more accurate gloss measurement of a sample under analysis.

Use of a single instruction set architecture (ISA) instruction for vector normalization

Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.

SMALL MULTIPLIER AFTER INITIAL APPROXIMATION FOR OPERATIONS WITH INCREASING PRECISION
20210208850 · 2021-07-08 ·

In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.

SMALL MULTIPLIER AFTER INITIAL APPROXIMATION FOR OPERATIONS WITH INCREASING PRECISION
20210208850 · 2021-07-08 ·

In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.