Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.

A display device which can display a clear image and can display an image with low power consumption is provided. The display device includes an arithmetic circuit having a function of generating first to third display data, a first display portion, and a second display portion. The arithmetic circuit has a function of detecting a color region and a gray-scale region of the generated first display data and generating the second display data corresponding to an image to be displayed on the first display portion and the third display data corresponding to an image to be displayed on the second display portion, on the basis of the detection results.

A display device which can display a clear image and can display an image with low power consumption is provided. The display device includes an arithmetic circuit having a function of generating first to third display data, a first display portion, and a second display portion. The arithmetic circuit has a function of detecting a color region and a gray-scale region of the generated first display data and generating the second display data corresponding to an image to be displayed on the first display portion and the third display data corresponding to an image to be displayed on the second display portion, on the basis of the detection results.

Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.

Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.

Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.