An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

An electronic device includes a coding module that determines whether a parameter of an artificial neural network is an outlier, depending on a value of the parameter and compresses the parameter by truncating a first bit of the parameter when the parameter is a non-outlier and truncating a second bit of the parameter when the parameter is the outlier, and a decoding module that decodes a compressed parameter.

An electronic device includes a coding module that determines whether a parameter of an artificial neural network is an outlier, depending on a value of the parameter and compresses the parameter by truncating a first bit of the parameter when the parameter is a non-outlier and truncating a second bit of the parameter when the parameter is the outlier, and a decoding module that decodes a compressed parameter.

A processor may include a set of primitive operators, receive a set of data-driven operators, at least one of the set of data-driven operators including a machine learning model, and receive an input-output data pair set. Based on a grammar specifying rules for linking the set of primitive operators and the set of data-driven operators, the processor may search among the set of primitive operators and the set of data-driven operators to find a symbolic model that fits the input-output data set.

According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.

According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for execution of a conditional statement by an arithmetic and/or bitwise unit. A computer program that comprises a conditional statement that comprises a Boolean condition is accessed. The Boolean condition is transformed into an arithmetic and/or bitwise expression of the Boolean condition. An arithmetic and/or bitwise expression of the computer program comprises the arithmetic and/or bitwise expression of the Boolean condition in place of the Boolean condition. The arithmetic and/or bitwise expression of the computer program is executed by an arithmetic and/or bitwise operation unit of a processor.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for execution of a conditional statement by an arithmetic and/or bitwise unit. A computer program that comprises a conditional statement that comprises a Boolean condition is accessed. The Boolean condition is transformed into an arithmetic and/or bitwise expression of the Boolean condition. An arithmetic and/or bitwise expression of the computer program comprises the arithmetic and/or bitwise expression of the Boolean condition in place of the Boolean condition. The arithmetic and/or bitwise expression of the computer program is executed by an arithmetic and/or bitwise operation unit of a processor.

A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.