Patent classifications
G06F8/433
AUTONOMOUS COMPUTE ELEMENT OPERATION USING BUFFERS
Techniques for task processing based on autonomous compute element operation using buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control is provided for the array of compute elements on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. An autonomous operation buffer is loaded with at least two operations contained in control words. The autonomous operation buffer is integrated in a compute element. A compute element operation counter coupled to the autonomous operation buffer is set. The compute element operation counter is integrated in the compute element. The at least two operations are executed using the autonomous operation buffer and the compute element operation counter. The operations complete autonomously from direct compiler control.
APPLICATION PROGRAMMING INTERFACE TO INDICATE EXECUTION OF GRAPH NODES
Apparatuses, systems, and techniques to facilitate execution graph control. In at least one embodiment, an application programming interface comprising one or more parameters is used to indicate which of one or more portions of graph code are to be performed.
Methods and apparatus to detect and annotate backedges in a dataflow graph
Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
Methods and systems for distributing instructions amongst multiple processing units in a multistage processing pipeline
Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.
METHODS AND SYSTEMS FOR DISTRIBUTING INSTRUCTIONS AMONGST MULTIPLE PROCESSING UNITS IN A MULTISTAGE PROCESSING PIPELINE
Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.
Implementing dependency injection via direct bytecode generation
A system includes a memory and a processor in communication with the memory. The processor is configured to process at least one application file and generate bytecode, responsive to processing the at least one application file, from the at least one application file prior to start-up time. The bytecode contains a metamodel and the metamodel controls dependency injection. Additionally, the metamodel is classified as at least one of a first class that is generated at start-up time, a second class that is generated as source files and compiled at compile time, and a third class that is generated directly as bytecode. The processor is also configured to store the bytecode associated with the third class of metamodel.
Generating compilable machine code programs from dynamic language code
Methods and systems describe providing a compilable machine code program from dynamic language code. First, the system receives a computer program consisting of code in a dynamic language. For each dynamic instruction within the code, the system: identifies all function calls within the code which may call the dynamic instruction; generates a super slice callgraph for all identified function calls for the dynamic instruction, including dependency relationships for instance variables and static variables within time constraints; and generates a set of slices for the dynamic instruction. The system then compiles and executes each slice to identify one or more values for each dynamic instruction. Next, the system updates the computer program such that each of at least a subset of the dynamic instructions is replaced with machine code instructions based on the corresponding values.
APPLICATION MODULE VERSION MANAGEMENT
Versions of an application are managed by receiving a request for a version of an application, retrieving, responsive to the received request, a version of a master application component based at least in part on version data that associates a version of the master application component with the version of the application, retrieving a relationship operable to relate the version of the master application component with a corresponding version of a first component on which the master application component depends for a function of the application, retrieving the corresponding version of the first component, responsive to the retrieving of the relationship, assembling the version of the application based at least in part on the retrieved version of the master component, the retrieved relationship, and the retrieved first component, and providing for an execution of the assembled version of the application.
METHOD AND SYSTEM FOR MACHINE LEARNING BASED UNDERSTANDING OF DATA ELEMENTS IN MAINFRAME PROGRAM CODE
Most of the existing production applications in different domains are still running on. Mainframe applications in production receive data from various resources and process these data within. Understanding the structure of input data and output data is extremely important. A method and system for machine learning based understanding of a plurality of data elements in a mainframe program code has been provided. The method discloses a machine learning model that understands the structure of data elements in a Mainframe program code. The model considered is a graph neural network based architecture model. The disclosed method replicates memory mapping happening in the application program environment. The method understands the structure of the data element and the impact created by each data element on other data elements in the application and interfacing applications. The disclosed solution serves as a building block in problems such as code translation, reverse engineering etc.
Firmware upgrade method and apparatus, and terminal
Embodiments disclose a firmware upgrade method and apparatus, and a terminal. The method includes: sequentially obtaining first upgrade data and operation instructions in all data blocks in a block differential upgrade package; converting first data into a second upgrade data in an image of an old firmware version according to the operation instruction; and controlling the first upgrade data and the second upgrade data to overwrite a to-be-upgraded data area in the image of the old firmware version. An operation of upgrading to an image of a new firmware version is completed in the image of the old firmware version based on the first upgrade data and the second upgrade data. In addition, in comparison with a conventional differential upgrade package, in the block differential upgrade package, a part or all of data in the conventional differential upgrade package is replaced with an operation instruction.