Patent classifications
G06F8/443
Implementing a type restriction that restricts to a non-polymorphic layout type or a maximum value
A type restriction contextually modifies an existing type descriptor. The type restriction is imposed on a data structure to restrict the values that are assumable by the data structure. The type restriction does not cancel or otherwise override the effect of the existing type descriptor on the data structure. Rather the type restriction may declare that a value of the data structure's type is forbidden for the data structure. Additionally or alternatively, the type restriction may declare that an element count allowable for a data structure's type is forbidden for the data structure. Type restriction allows optionality (where only a singleton value for a data structure is allowed), empty sets (where no value for a data structure is allowed), and multiplicity (where only a limited element count for a data structure) to be injected into a code set independent of data type. Type restriction allows certain optimizations to be performed.
Sparsity uniformity enforcement for multicore processor
Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.
Implementing dependency injection via direct bytecode generation
A system includes a memory and a processor in communication with the memory. The processor is configured to process at least one application file and generate bytecode, responsive to processing the at least one application file, from the at least one application file prior to start-up time. The bytecode contains a metamodel and the metamodel controls dependency injection. Additionally, the metamodel is classified as at least one of a first class that is generated at start-up time, a second class that is generated as source files and compiled at compile time, and a third class that is generated directly as bytecode. The processor is also configured to store the bytecode associated with the third class of metamodel.
FAST SEARCH FOR SEARCH STRING INSTRUCTIONS
One or more computer processors receive a pattern string comprising a pointer to a pattern search point and a string comprising a pointer to a search point; determine a plausible search point within the string for the pattern character; execute a search string (SRST) instruction with the determined search point and the pattern character; compute a pattern offset comprising a difference between a first occurrence of the determined pattern character located within the pattern string but not in the correct position and a current pattern character position; execute a subsequent SRST instruction with the current pattern character position and the computed offset set as a new search point; and responsive to identifying all pattern characters in the correct position within the string based on the executed subsequent SRST instruction, transmit memory address associated with a substring comprised of the string and corresponding pattern characters in the correct position.
PROCESSING DEVICE AND METHOD OF USING A REGISTER CACHE
A processing device is provided which comprises memory, a plurality of registers and a processor. the processor is configured to execute a plurality of portions of a program, allocate a number of the registers per portion of the program such that a number of remaining registers are available as a register cache and transfer data between the number of registers, which are allocated per portion of the program, and the register cache. The processor loads data to the allocated registers to execute a portion of the program, stores data, resulting from execution of the portion, in the register cache, reloads the data in the allocated registers and executes another portion of the program using the data reloaded to the allocated registers and A called function uses the number of allocated registers, which is less than an architectural limit of registers allocated per portion of the program.
Generating compilable machine code programs from dynamic language code
Methods and systems describe providing a compilable machine code program from dynamic language code. First, the system receives a computer program consisting of code in a dynamic language. For each dynamic instruction within the code, the system: identifies all function calls within the code which may call the dynamic instruction; generates a super slice callgraph for all identified function calls for the dynamic instruction, including dependency relationships for instance variables and static variables within time constraints; and generates a set of slices for the dynamic instruction. The system then compiles and executes each slice to identify one or more values for each dynamic instruction. Next, the system updates the computer program such that each of at least a subset of the dynamic instructions is replaced with machine code instructions based on the corresponding values.
METHOD AND DEVICE FOR MANAGING ACCESSES OF MULTIPLE SOFTWARE COMPONENTS TO SOFTWARE INTERFACES
A method for managing accesses of multiple software components to software interfaces. In the method, a temporal allocation of the software components to the software interfaces is calculated statically based on requirements of the software components with respect to the software interfaces. The allocation is optimized continuously in light of an observed runtime behavior of the software components.
IDENTIFY, SUGGEST, AND AUTO-IMPLEMENT BEST PRACTICES FOR REQUIREMENT SPECIFIC SOFTWARE DEVELOPMENT
An approach is disclosed that receives a code segment from a source code file. The received code segment is inputted to a trained knowledge manager from which one or more comparable code segments are received. Each of the comparable code segments are identified as having similar functionality as the selected code segment and each of the comparable code segments has a set of metadata. The metadata is used to select one of the comparable code segments and this selected code segment is used to replace the original code segment in the source code file.
Data structure allocation into storage class memory during compilation
A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.
Dynamic tracer message logging based on bottleneck detection
A monitoring system monitors processing of incoming messages by an application, and logs data related to performance of the application. The application includes a plurality of checkpoints, and the monitoring system logs data upon each message traversing the checkpoints in the application. The monitoring system is configured to dynamically modify checkpoints within the application based on latency detection of portions of the application, resulting in improved granularity/resolution of the data collected from congested portions of the application, and reducing the performance penalty of the monitoring system from portions of the application that are not congested.