Systems, apparatuses and methods may provide for technology that generates a first compiler output based on input code that includes dynamically typed variable information and generates a second compiler output based on the input code, wherein the second compiler output includes type check code to verify one or more type inferences associated with the first compiler output. The technology may also execute the first compiler output and the second compiler output in parallel via different threads.

The present disclosure relates to a method for automatically optimizing a program based on reinforcement learning. The method for automatically optimizing a program based on reinforcement learning includes (a) receiving an input for a source program, which includes a fixed parameter and variable parameter, (b) generating the source program based on the received input, (c) converting the source program into an object program, (d) executing the converted object program to measure a performance of the executed object program, (e) inputting the variable parameter and the measured performance into a machine learning model, and outputting a variation of the variable parameter, and (f) regenerating a source program reflecting the variation of the variable parameter.

A computation graph is accessed. In the computation graph, operations to be performed are represented as interior nodes, inputs to the operations are represented as leaf nodes, and a result of the operations is represented as a root. Selected sets of the operations are combined to form respective kernels of operations. Code is generated execute the kernels of operations. The code is executed to determine the result.

Example implementations relate to processing of retail offerings and retail rules for implementation in a retail appliance. For example, retail rules and retail offerings may be translated into a retail offer domain-specific language (DSL). The translated retail rules and retail offerings may be expressed as constraints according to a satisfiability module theory (SMT) language. A hardware-optimized description of the translated retail rules and retail offerings may be generated that satisfy the constraints, and computer-executable instructions may be generated, based on the hardware-optimized description.

Examples described herein relate to technologies to execute a compiler for a process to be executed by one or more graphics processing units (GPUs) to compile the process based on run-time profile guided optimization (PGO). In some examples, the process is compiled based on run-time PGO is based on profile data versioned by application, driver, and GPU version; previously generated profile data; a subset of draws to profile and optimize; or other factors.

Methods and systems for selective optimization include determining that a method, compiled with a speculative optimization, is executed with a frequency that exceeds a first threshold value, such that runtime recompilation of the method causes user delays. The method is recompiled without the speculative optimization, to avoid recompilation delays during runtime. The recompiled method is then executed.

A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.

The specification unit 3 specifies a description part of an arithmetic expression that represents loop processing from an input source program. The generation unit 4 generates arithmetic expressions that represent executing, when a remainder when dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number, and executing loop processing with the designated unroll stage number after the processing of one loop. The replacement unit 5 replaces the arithmetic expression of the description part specified by the specification unit 3 with the arithmetic expressions generated by the generation unit 4.

Systems, apparatuses and methods may be associated with a first computing device and provide for identifying performance metrics. The performance metrics are associated with execution of a first function on at least one second computing device. The systems, apparatuses and methods aggregate the performance metrics to generate aggregated performance metrics, determine that the aggregated performance metrics meet a threshold and compile code associated with the first function in response to the aggregated performance metrics being determined to meet the threshold.

A method and apparatus are disclosed for finding overlong source code segments (e.g., methods) by evaluating input source code segments for a plurality of predetermined code metric values in order to identify candidate source code segments (e.g., non-autogenerated methods) which do not meet a first code metric value and to assess each candidate source code segment against a second code metric value to identify different sets of candidate source code segments (e.g., test methods and normal methods) so that each set of candidate source code segments may be assessed against a tailored set of code length thresholds to identify any overlong source code segment having a code length which meets or exceeds at least two of the tailored set of code length thresholds.