Techniques for implementing tenancy isolation for entities are disclosed. In some embodiments, a computer system performs operations comprising: compiling a software project having one or more source code files, the source code file(s) comprising entity classes, each one of the entity classes having a corresponding entity class definition comprising a tenancy isolation annotation that is defined in a software library, the compiling of the software project comprising compiling the entity classes; and enhancing the compiled entity classes based on the entity class definitions of the compiled entity classes comprising the tenancy isolation annotation, the enhancing the compiled entity classes comprising adding a tenancy filter to the corresponding entity class definitions of the compiled entity classes, the tenancy filter being configured to apply tenancy isolation to entity instances of the compiled entity classes in a relational database.

A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.

Certain example embodiments relate to techniques for use with mainframe computing systems that include both general-purpose processors (e.g., CPs) and special-purpose processors that can be used to perform only certain limited operations (e.g., zIIPs). Certain example embodiments automatically help these special-purpose processors perform user exits and other routines thereon, rather than requiring those operations to be performed on general-purpose processors. This approach advantageously can improve system performance when executing programs including these user exits and other routines, and in a preferred embodiment, it can be accomplished in connection with a suitably-configured user exit daemon. In a preferred embodiment, the daemon and its clients can use a user exit property table or the like to communicate with one another about the state of each user exit or other routine that has been analyzed, classified, and possibly modified.

An embodiment relates to an artificial intelligence inference apparatus and method. The embodiment provides an artificial intelligence inference method, and may include converting an application based on a previously learned neural network into executable code in a high-level language independent of a learning framework, separating the executable code into General-Purpose Language (GPL) code and Domain-Specific Language (DSL) code depending on whether an acceleration operation is required, and generating target code optimized for hardware from the separated GPL code and DSL code.

A method and apparatus are disclosed for enhancing operable functionality of input source code files from a software program by identifying a first code snippet and a first library function which generate similar outputs from a shared input by parsing each and every line of code in a candidate code snippet to generate a templatized code snippet data structure for the first code snippet, and then testing the templatized code snippet data structure against extracted library function information to check for similarity of outputs between the first code snippet and the first library function in response to a shared input so that the developer is presented with a library function recommendation which includes the first code snippet, the first library function, and instructions for replacing the first code snippet with the first library function.

A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

The disclosure invention provides a method for executing a program compiled for a source architecture on a machine having a different target architecture, a non-transitory computer readable medium configured to store instructions for performing such a method, and a system for performing such a method.

A mixed mode programming method permitting users to program with graphical coding blocks and textual code within the same programming tool. The mixed mode preserves the advantages of graphical block programming while introducing textual coding as needed for instructional reasons and/or for functional reasons. Converting a graphical code block or group of blocks to a textual block lets the user see a portion of the textual code in the context of a larger program. Within one programming tool the mixed mode method allows users to learn programming and build purely graphical blocks; then transition into mixed graphical and textual code and ultimately lead to their ability to program in purely textual code. The mixed mode further allows users to program using any combination of drag-and-drop graphical blocks and typed textual code in various forms.

The invention relates to distributed ledger technologies such as consensus-based blockchains. Computer-implemented N methods for reducing arithmetic circuits derived from smart contracts are described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a programmatic set of conditions encoded in a second programming language. The programmatic set of conditions is precompiled into precompiled program code. The precompiled program code is transformed into an arithmetic circuit. The arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.

Quantum field-programmable analog arrays (FPAAs) may be useful in solving differential equations. For example, a quantum FPAA may comprise: an array of computational analog blocks (CABs) configured to perform a mathematical operation; and an interconnection network connecting the CABs, the interconnection network comprising communication paths and switches. Said quantum FPAAs may be useful in integrated chips, computing systems, and related methods.