Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.

Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.

A multi-core processor includes a primary processor core and a secondary processor core coupled to the primary processor core. The primary processor core has first instruction space, and the secondary processor core has second instruction space. The primary processor core is configured to execute a first code segment in a target program, where the target program further includes a second code segment, the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space, and send an address of the second code segment to the secondary processor core through a configuration interface of the secondary processor core.

There is provided methods and apparatus to improve runtime by computer programs at compilation time. A compiler analyzes code to be translated into machine executable instructions to identify overloaded functional units of the target processor, and replaces instructions scheduled on the overloaded functional unit to an idle unit using functionally equivalent operations on the idle unit. The replacement instructions may be taken from an instruction replacement library comprising function calls that implement functionality of a functional unit of the target processor on another functional unit of the target processor.

The subject technology provides for dynamic task allocation for neural network models. The subject technology determines an operation performed at a node of a neural network model. The subject technology assigns an annotation to indicate whether the operation is better performed on a CPU or a GPU based at least in part on hardware capabilities of a target platform. The subject technology determines whether the neural network model includes a second layer. The subject technology, in response to determining that the neural network model includes a second layer, for each node of the second layer of the neural network model, determines a second operation performed at the node. Further the subject technology assigns a second annotation to indicate whether the second operation is better performed on the CPU or the GPU based at least in part on the hardware capabilities of the target platform.

The invention relates to distributed ledger technologies such as consensus-based blockchains. Computer-implemented N methods for reducing arithmetic circuits derived from smart contracts are described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a programmatic set of conditions encoded in a second programming language. The programmatic set of conditions is precompiled into precompiled program code. The precompiled program code is transformed into an arithmetic circuit. The arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.

An offload server includes: an application code analysis section configured to analyze a source code of an application and detect external library calls included in the source code as replacement sources; a replacement function detection section configured to retrieve libraries and IP cores from a code pattern database by using the detected external library calls as keys, as replacement-destination libraries/IP cores; and a replacement processing section configured to replace processing descriptions of the replacement sources with processing descriptions of the replacement-destination libraries/IP cores retrieved by the replacement function detection section and to generate interfaces of a CPU to the replacement-destination libraries/IP cores.

A method includes analyzing a dataflow graph representing data dependencies between operators of a dataflow application to identify a plurality of candidate groups of the operators. Based on characteristics of a given hardware accelerator and the operators of a given candidate group of the plurality of candidate groups, determining whether the operators of the given candidate group are to be combined. In response to determining that the operators of the given candidate group are to be combined, retrieving executable binary code segments corresponding to the operators of the given candidate group, generating a unit of binary code including the executable binary code segments and metadata representing an execution control flow among the executable binary code segments, and dispatching the unit of code to the given hardware accelerator for execution of the unit of code.

A compile method for a neural network, the compile method includes receiving data related to the neural network, generating a grouped layer by grouping layers comprised in the neural network based on the data, generating a set of passes executable in parallel based on a dependency between a plurality of passes to process the neural network, generating a set of threads performing a plurality of optimization functions based on whether optimization operations performed by the optimization functions is performed independently for the layers, respectively, or sequentially based on a dependency between the layers, and performing compilation in parallel based on the grouped layer, the set of passes, and the set of threads.

Various arrangements for facilitating smart television content receivers in a local network are provided. A primary television receiver executing a first operating system can receive audio data including human voice from a voice enabled remote control. The primary television receiver can transmit the audio data to a secondary television receiver executing a second operating system and that includes a voice command component. The secondary television receiver can convert the audio data into voice command data and transmit the voice command data to the primary television receiver. The primary television receiver can transmit the voice command data to a voice processing server via the Internet and receive, in response, a command generated based on the voice command data. The primary television receiver can transmit the command to the secondary television receiver. The voice command component can then control an operation of the secondary television receiver based on the command.