Abstract Syntax Trees (ASTs) are generated using the source code of a programming language that include information relating to the structure of the program. The generation of the ASTs may be performed in parallel. The types are split into a number of modules (e.g. configurable) that form an assembly. During the different stages of the compilation process, each module may be compiled in parallel. As the different modules are being compiled (e.g. in parallel), compiler metadata from the different modules may be written to a repository accessible by the different compilation processes. After flowing through the compilation pipeline, each of the enriched ASTs are used for code generation where they are transformed into the target language (e.g. a code stream that can be executed on hardware). The executable code is then stored as part of the assembly. The storage of the code may also be performed in parallel.

Provided is a multi-module compilation system for generating execution codes for each of modules in a module system. The multi-module compilation system may include a module identifier configured to analyze a program code of the module system and to identify target modules that execute the program code, a module code generator configured to divide the program code into module codes for each of the target modules and to generate the module codes, and a compiler configured to compile the module codes and to generate execution codes for each of the target modules.

Provided is a module system including a plurality of modules communicating with each other. The module system may include a master module configured to communicate with an external device, and at least one sub-module connected to a network to perform a data communication with the master module. The master module may transmit update data to a target sub-module requiring updating of data associated with an operation of the target sub-module among the at least one sub-module, via the network.

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Systems and methods described herein relate to the execution of locking transactions in a blockchain system. In the context of smart contracts, it may be advantageous to have a public record (e.g., recorded on a blockchain) of a proof of correct execution of a circuit published by a worker and the verification key, thereby allowing anyone (e.g., nodes of the blockchain) to verify validity of the computation and proof. However, there are challenges to recording large blocks of data (e.g., large keys that may comprise multiple elliptic curve points) on the blockchain. For example, in a Bitcoin-based blockchain network, a protocol that utilizes standard transactions may be constrained to locking scripts and unlocking scripts that are collectively no t larger than a first predetermined size limit, and the size of a redeem script (if utilized) may be limited to being no more than a second predetermined size limit

Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.

Systems and methods are described that implement a tool chain which receives original software source code, analyzes the code and divides the code into modules that run optimally on the available heterogeneous resources. For example, the toolchain system segments original source code into code segments, and determine the specialized processor resource, such as a digital signal processing (DSP) processor, Field Programming Gate Array (FPGA), Graphical Processing Unit (GPU), and the like, that most optimally performs computations of the particular code segment. A parsing engine determines the processor of the heterogenous resources, based on a set of rules and/or a trained classifier (e.g., a trained machine learning model). New code segments can be generated that can be executed on the determined type of processor. Further, the system enables application programming interfaces (APIs) that can interface the new code segment with other generated code segments and/or some portions of the original code.

The present application relates to the technical field of computer, and provides a method, a device and a terminal apparatus for code execution and a computer readable storage medium. The present application provide an identifier for parallel processing, and the user can use the parallel processing identifier to identify code statements that need to be processed in parallel in advance. During the execution of the code, when the parallel processing identifier is found in the current code statement to be executed, the task to be processed indicated by the current code statement to be executed is distributed to a preset grid computing system Perform multi-thread parallel processing. During the execution of this code statement, the user can continue to execute the next code statement.

A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.

A method for generating a program to run on multiple tiles. The method comprises: receiving an input graph comprising data nodes, compute vertices and edges; receiving an initial tile-mapping specifying which data nodes and vertices are allocated to which tile; and determining a subgraph of the input graph that meets one or more heuristic rules. The rules comprises: the subgraph comprises at least one data node, the subgraph spans no more than a threshold number of tiles in the initial tile-mapping, and the subgraph comprises at least a minimum number of edges outputting to one or more vertices on one or more other tiles. The method further comprises adapting the initial mapping to migrate the data nodes and any vertices of the determined subgraph to said one or more other tiles.