G06F8/451

SPARSITY UNIFORMITY ENFORCEMENT FOR MULTICORE PROCESSOR

Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.

SMART TV OPERATING SYSTEM ARRANGEMENTS FOR LOCAL NETWORK CONNECTED TELEVISION RECEIVERS
20230336811 · 2023-10-19 ·

Various arrangements for facilitating smart television content receivers are provided. A primary television receiver (PTR) having a first operating system may be configured to receive digital content from a remote content provider and distribute the content to one or more devices in response to a request for the content. A secondary television receiver (STR) configured to be in communication with a PTR and having a second operating system may be configured to receive the digital content from the PTR and provide the content to a display for presentation. The STR may include a first software stack including a first inter-process communication (IPC) mechanism, and a second software stack including the first IPC mechanism and a second IPC mechanism. The first IPC may support communication within the first stack as well as between the first stack and the second stack. The second IPC may support communication within the second stack.

SYSTEM FOR SECURING VERIFICATION KEY FROM ALTERATION AND VERIFYING VALIDITY OF A PROOF OF CORRECTNESS

The invention relates to distributed ledger technologies such as consensus-based blockchains. A blockchain transaction may include digital resources that are encumbered by a locking script that encodes a set of conditions that must be fulfilled before the encumbered resources may be used (e.g., transferring ownership/control of encumbered resources). A worker (e.g., a computer system) performs one or more computations to generate a proof, which is encoded as part of an unlocking script. A verification algorithm may utilize the proof, a verification key, and additional data such as a cryptographic material associated with the worker (e.g., a digital signature) to verify that digital assets of the transaction should be transferred. As a result of the validation of this transaction, any third party is able to check the contract was executed corrected rather than re-executing the contract, thus saving computational power.

Programming a Coarse Grained Reconfigurable Array through Description of Data Flow Graphs

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

DYNAMIC PARTITION CUSTOMIZATION METHOD AND APPARATUS, AND DEVICE

The present application provides a dynamic partition customization method and apparatus, and a device. The method includes: generating a plurality of original equipment manufacturer (OEM) image files corresponding to requirements of a plurality of different users at compile time; generating a scatter loading file recording OEM image sub-file segments according to a super image file in a super partition; according to change of a requirement of a user among the plurality of different users, downloading an OEM image sub-file segment corresponding to the changed requirement; and generating a super partition customization file according to the scatter loading file and the OEM image sub-file segment corresponding to the changed requirement.

System and method of populating an instruction word
11755528 · 2023-09-12 · ·

A methodology for populating an instruction word for simultaneous execution of instruction operations by a plurality of ALUs in a data path is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first selecting a first available instruction node from the dependency graph; first assigning the selected first available instruction node to the instruction word; second selecting any available dependent instruction nodes that are dependent upon a result of the selected first available instruction node and do not violate any predetermined rule; second assigning to the instruction word the selected any available dependent instruction nodes; and updating the dependency graph to remove any instruction nodes assigned during the first and second assigning from further consideration for assignment.

Method and apparatus for functional unit balancing at program compile time

There is provided methods and apparatus to improve runtime by computer programs at compilation time. A compiler analyzes code to be translated into machine executable instructions to identify overloaded functional units of the target processor, and replaces instructions scheduled on the overloaded functional unit to an idle unit using functionally equivalent operations on the idle unit. The replacement instructions may be taken from an instruction replacement library comprising function calls that implement functionality of a functional unit of the target processor on another functional unit of the target processor.

System for securing verification key from alteration and verifying validity of a proof of correctness

The invention relates to distributed ledger technologies such as consensus-based blockchains. A blockchain transaction may include digital resources that are encumbered by a locking script that encodes a set of conditions that must be fulfilled before the encumbered resources may be used (e.g., transferring ownership/control of encumbered resources). A worker (e.g., a computer system) performs one or more computations to generate a proof, which is encoded as part of an unlocking script. A verification algorithm may utilize the proof, a verification key, and additional data such as a cryptographic material associated with the worker (e.g., a digital signature) to verify that digital assets of the transaction should be transferred. As a result of the validation of this transaction, any third party is able to check the contract was executed corrected rather than re-executing the contract, thus saving computational power.

SYSTEM AND METHOD FOR PERFORMING PARALLEL AND DISTRIBUTED ANALYSIS OF PROGRAM CODE TO GENERATE DEPENDENCY GRAPHS FOR EXECUTING EXTRACT TRANSFORM LOAD TRANSFORMATIONS

Embodiments of the present invention provide a system for performing parallel and distributed analysis of program code to generate directed graphs for executing extract transform load transformations. The system is configured for identifying that a user has initiated a request for analysis of a program code, via a compiler, extracting a syntax tree associated with the program code from the compiler, performing parallel and distributed analysis of the program code based on the syntax tree, generating a directed graph based on performing parallel and distributed analysis of the program code, and storing the directed graph in a cache memory.

Unified optimization for convolutional neural network model inference on integrated graphics processing units

Techniques for optimizing and deploying convolutional neural network (CNN) machine learning models for inference using integrated graphics processing units are described. A model compilation system optimizes CNN models using optimized vision-specific operators as well as both graph-level tuning and tensor-level tuning to explore the optimization space for achieving heightened performance. The model compilation system may also implement a heuristic-based two-stage technique for falling back certain operators of CNN models to use CPUs when needed or otherwise beneficial.