Techniques to partition a neural network model for serial execution on multiple processing integrated circuit devices are described. An initial partitioning of the model into multiple partitions each corresponding to a processing integrated circuit device is performed. For each partition, an execution latency is calculated by aggregating compute clock cycles to perform computations in the partition, and weight loading clock cycles determined based on a number of weights used in the partition. The amount of data being outputted from the partition is also determined. The partitions can be adjusted by moving computations from a source partition to a target partition to change execution latencies of the partitions and the amount of data being transferred between partitions.

A software update management apparatus includes a storage unit adapted to divide a network into one or more blocks and store block management information indicating whether each of network devices belonging to each of the resulting blocks is an active device or a standby device; an update instruction receiving unit adapted to receive software update instructions; a software update information generating unit adapted to generate software update information; a software updating unit adapted to perform software update processes after transferring traffic to standby devices in same blocks as respective active devices when it is determined that the network devices are active devices according to the software update information and thereby perform the software update processes for active devices or standby devices in different blocks in parallel.

A method of protocol processing including a main program code that has one or more code segments and instructions for processing different protocol elements of a data packet stream of a transport protocol is disclosed herein. The method includes assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code; and compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors.

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

The invention provides systems and methods for converting high level source code into an arithmetic circuit which represents the functionality expressed in the source code. The invention comprises a translation/interpretation component for performing this conversion. In a preferred embodiment, the source code is a smart contract such as those used in relation to a blockchain platform. The invention could be used in relation to the Bitcoin network, for example. A method in accordance with an embodiment comprises the steps of: processing a portion of high level source code (e.g. a smart contract) to generate an arithmetic circuit. The arithmetic circuit comprises one or more arithmetic gates arranged to represent at least some of the functionality expressed in the source code. The processing involves evaluating one or more constants provided in the source code to produce one or more expressions that include Boolean and/or arithmetic operators. The arithmetic circuit comprises n-bit wires connected to arithmetic gates; it can be used to provide a hardware and/or software circuit. The arithmetic circuit can be used to generate a quadratic program which can be executed upon a processor.

Various arrangements for facilitating smart television content receivers are provided. A primary television receiver (PTR) having a first operating system may be configured to receive digital content from a remote content provider and distribute the content to one or more devices in response to a request for the content. A secondary television receiver (STR) configured to be in communication with a PTR and having a second operating system may be configured to receive the digital content from the PTR and provide the content to a display for presentation. The STR may include a first software stack including first processes and a first inter-process communication (IPC) mechanism, and a second software stack including second processes and a second IPC mechanism. The first processes may use the first IPC to communicate with the second processes. The second processes may use the second IPC to communicate with others of the second processes.

Disclosed in some examples, are systems, methods, devices, and machine readable mediums which use improved dynamic programming algorithms to pack conditional branch instructions. Conditional code branches may be modeled as directed acyclic graphs (DAGs) which have a topological ordering. These DAGs may be used to construct a dynamic programming table to find a partial mapping of one path onto the other path using dynamic programming algorithms.

Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.

Various arrangements for facilitating smart television content receivers in a local network are provided. A primary television receiver executing a first operating system can receive audio data including human voice from a voice enabled remote control. The primary television receiver can transmit the audio data to a secondary television receiver executing a second operating system and that includes a voice command component. The secondary television receiver can convert the audio data into voice command data and transmit the voice command data to the primary television receiver. The primary television receiver can transmit the voice command data to a voice processing server via the Internet and receive, in response, a command generated based on the voice command data. The primary television receiver can transmit the command to the secondary television receiver. The voice command component can then control an operation of the secondary television receiver based on the command.

Methods, methods, and non-transitory, machine-readable media to facilitate streaming in a local network with a client-server architecture are disclosed. A primary media device may be configured to: operate as a server in a local network, receive first audio/video (A/V) content via an Internet connection, and receive second A/V content via a satellite network connection. Each secondary media device of a set of one or more secondary media devices may be configured to: operate as a client with respect to the primary media device in the local network, receive the first A/V content from the primary media device, receive the second A/V content from the primary media device, and provide the first A/V content and the second A/V content to at least one television of a set of one or more televisions.