A method for generating an executable program to run on one or more processor modules. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and edges; and compiling the graph into an executable program including one or more types of multi-access instruction each of which performs at least two memory access (load and/or store) operations in a single instruction. The memory on each processor module comprises multiple memory banks whereby the same bank cannot be accessed by different load or store operations in the same instruction. The compilation comprises assigning instances of the multi-access instructions to implement at least some of the graph edges, and allocating the data to memory addresses within different ones of the banks. The allocating is performed subject to one or more constraints, including at least that different load/store operations should not access the same memory bank in the same instruction.

Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.

An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

Embodiments of the present invention disclose a method, a computer program product, and a computer system for mapping components of non-distributed environments to distributed environments. A computer receives a data pipeline configured for a non-distributed environment and identifies one or more bottleneck components of the data pipeline. In addition, the computer converts data used in the pipeline to a format compatible with a distributed environment and installs the necessary computing libraries necessary for operating the pipeline within the distributed environment. The computer further converts the code of the pipeline to a code that is compatible with the distributed environment and optimizes components of the pipeline for use in the distributed environment.

A computer-implemented method is provided for compilation rescheduling from among four compilation levels comprising level 1, level 2, level 3, and level 4 on a parallel distributed computing framework running processes for a plurality of jobs of a virtual machine. The method bypasses a program analysis overhead that includes measuring a compiled method execution time by identifying completed compilation levels of a Just In Time compilation. The method finds a repetition of a same process in the processes for the plurality of jobs of the virtual machine from profiles by comparing main class names, virtual machine parameters, and Jar file types therein. The method applies a compilation scheduling for the same process a next time the same process runs based on a result of the checking the transition, by (i) compiling at the level 1 at least some methods for the same process responsive to the virtual machine finishing without compiling the at least some methods for the same process at the level 4 after compiling the at least some of the methods at a level in between the level 1 and the level 4, and (ii) compiling at the level 4 at least a subset of the methods earlier than an original scheduled time responsive to at least the subset of the methods compiled at the level 4 being infrequently invoked below a threshold amount.

Various arrangements for facilitating smart television content receivers are provided. A primary television receiver (PTR) having a first operating system may be configured to receive digital content from a remote content provider and distribute the content to one or more devices in response to a request for the content. A secondary television receiver (STR) configured to be in communication with a PTR and having a second operating system may be configured to receive the digital content from the PTR and provide the content to a display for presentation. The STR may include a first software stack including a first inter-process communication (IPC) mechanism, and a second software stack including the first IPC mechanism and a second IPC mechanism. The first IPC may support communication within the first stack as well as between the first stack and the second stack. The second IPC may support communication within the second stack.

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

Various arrangements for facilitating smart television content receivers are provided. A primary television receiver (PTR) having a first operating system may be configured to receive digital content from a remote content provider and distribute the content to one or more devices in response to a request for the content. A secondary television receiver (STR) configured to be in communication with a PTR and having a second operating system may be configured to receive the digital content from the PTR and provide the content to a display for presentation. The STR may include a first software stack including first processes and a first inter-process communication (IPC) mechanism, and a second software stack including second processes and a second IPC mechanism. The first processes may use the first IPC to communicate with the second processes. The second processes may use the second IPC to communicate with others of the second processes.

Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.