An operation assistance system receives selection of a first procedure in a procedure manual including a plurality of procedures relating to an operation of an operation target. The operation assistance system displays an estimation structure obtained by structuring at least part of the first procedure based on an abstraction structure obtained by structuring a second abstraction procedure included in a first abstraction procedure corresponding to the first procedure and the selected first procedure.

Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.

An automatic differentiation (AD) technique and implementation processes multi-physics solver code entirely on graphics processing units (GPUs) to automatically differentiate one or more outputs of the code with respect to one or more inputs. The technique provides a factory framework that ingests arbitrarily complex solver code to produce a version of the code that is automatically differentiated (AD code) and mapped to the GPUs. The technique provides a derivative of the solver code output with respect to the inputs that enables analysis of the output of the computed solver code with initially provided inputs coherent with sensitivity analysis of that output as the inputs are changed. The adjoint information derived from solver code execution (AD code) computed by the AD technique may also be used to estimate one or more estimates of the numerical error in a solution to the physical simulation.

An information processing method executed by a computer, the method includes executing a target program to acquire number of executions for each of a plurality of program codes; selecting a combination of program codes related to a plurality of assignment statements from among program codes related to assignment statements having a higher number of executions based on the acquired number of executions; when the target program is changed, executing the changed target program to calculate an execution accuracy and an operation time so that parallel processing using an SIMD operation function is executed for each of the program codes related to the plurality of assignment statements included in the selected combination; and searching for the combination so that the calculated execution accuracy and operation time satisfy a predetermined condition.

A computing system includes a compatibility graph builder to generate a compatibility graph based on a dependency graph representing program source code, where the compatibility graph indicates compatibility relationships between operations represented in the dependency graph, a clique generator coupled with the compatibility graph builder to generate a set of candidate vector packings based on the compatibility relationships indicated in the compatibility graph, a set cover generator coupled with the clique generator to select a subset of vector packings from the set of candidate vector packings, and a vector code generator coupled with the set cover generator to generate the vector code based on the selected subset of vector packings.

User input is received specifying components of a graph-based program specification. User input is received specifying links, at least some connecting an output port of an upstream component to an input port of a downstream component. The graph-based program specification is processed to identify one or more subsets of the components, including: identifying one or more subset entry points and one or more subset exit points that occur between components in different subsets based at least in part on data processing characteristics of linked components, and forming the subsets based on the identified subset entry points and exit points. A visual representation of the formed subsets is rendered within a user interface. Prepared code is generated for each formed subset that when used for execution by a runtime system causes processing tasks corresponding to the components in each formed subset to be performed.

A graph-based program specification includes: a plurality of components, each corresponding to a processing task and including one or more ports, including scalar data ports for sending or receiving a single data element and collection data ports for sending or receiving a collection of multiple data elements; and one or more links, each connecting an output port of an upstream component to an input port of a downstream component. Prepared code is generated representing subsets of the plurality of components, including: identifying one or more subset boundaries, including identifying one or more links connecting a collection data port of a component to a scalar data port of a component; forming the subsets based on the identified subset boundaries; and generating prepared code for each formed subset that when used for execution by a runtime system causes processing tasks corresponding to the components in each formed subset to be performed.

Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.

Process for the automatic generation of parallel code, at a high level of abstraction, executable on electronic calculators having heterogeneous multi-core or many-core architectures.

Disclosed is a multi-device based inference method and apparatus, where the multi-device based inference method includes receiving information related to operation devices performing an operation included in a neural network and a graph corresponding to the neural network, obtaining a size of an output of the operation in a forward direction of the graph based on the information and the graph, dividing an input of the operation in a backward direction of the graph based on the information, the graph, and the size of the output, and performing an inference based on the divided input.