An apparatus includes a processor and a storage storing instructions causing the processor to determine whether an analysis routine is multi-threaded and calls a library function of a non-threadsafe library, and if so, causes the processor to: instantiate an analysis process for executing the analysis routine on multiple threads; instantiate an instance of the library for execution within a isolated library process; instantiate another instance of the library for execution within another isolated library process; retrieve library metadata providing a function prototype of the library function; employ the function prototype to generate an instance of a bridge routine to enable a call from the analysis routine on a first thread to the library function; employ the function prototype to generate another instance of the bridge routine to enable a call from the analysis routine on a second thread to the library function; and begin execution of the analysis routine.

Provided is a module system including a plurality of modules communicating with each other. The module system may include a master module configured to communicate with an external device, and at least one sub-module connected to a network to perform a data communication with the master module. The master module may transmit update data to a target sub-module requiring updating of data associated with an operation of the target sub-module among the at least one sub-module, via the network.

Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus.

Techniques for detecting a data race condition between multiple execution engines of an integrated circuit device are provided. Computations and data movements involving execution engines of an integrated circuit may be described with a flow graph, where graph nodes represent computation or data movement operations and graph edges represent dependencies between the operations. When a graph has incorrect dependencies, data races may result. To detect data race conditions, compiler-generated vector clocks that track the relationships of operations performed by various execution engines may be used to determine concurrent operations between nodes of different execution engines, and memory access patterns for the operations may be compared to determine if the concurrent operations access the same memory address.

Data are maintained in a distributed computing system that describe a graph. The graph represents relationships among items. The graph has a plurality of vertices that represent the items and a plurality of edges connecting the plurality of vertices. At least one vertex of the plurality of vertices includes a set of label values indicating the at least one vertex's strength of association with a label from a set of labels. The set of labels describe possible characteristics of an item represented by the at least one vertex. At least one edge of the plurality of edges includes a set of label weights for influencing label values that traverse the at least one edge. A label propagation algorithm is executed for a plurality of the vertices in the graph in parallel for a series of synchronized iterations to propagate labels through the graph.

A method of simulating codes that form a program configured to control a control target includes causing a processor to execute the following: first-setting a first process of executing a simulation of an operation of a code group excluding a specific code among the codes; second-setting a second process of executing a simulation of an operation of a specific model obtained by modeling the specific code; first-simulating, in the first process, a first simulation of a code preceding the specific code in the code group; second-simulating, in the second process, a second simulation of the specific model through use of an execution result of the first simulation by inter-process communication between the first process and the second process; and third-simulating, in the first process, a third simulation of a code succeeding the specific code through use of an execution result of the second simulation by the inter-process communication.

A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

The embodiments of the present disclosure provide a method, an apparatus, a device and a medium for processing topological relation of tasks. The method includes: extracting at least one execution element from each of processing tasks based on a topological relation recognition rule; determining a dependency relation among the processing tasks according to content of the execution element of each processing task; and determining a topological relation among the processing tasks according to the dependency relation among the processing tasks.

A coarse-grained reconfigurable (CGR) processor comprises a first network and a second network; a plurality of agents coupled to the first network; an array of CGR units coupled together by the second network; and a tile agent coupled between the first network and the second network. The tile agent comprises a plurality of links, a plurality of credit counters associated with respective agents of the plurality of agents, a plurality of credit-hog counters associated with respective links of the plurality of links, and an arbiter to manage access to the first network from the plurality of links based their associated credit-hog counters. Furthermore, a credit-hog counter of the plurality of credit-hog counters changes in response to processing a request for a transaction from its associated link.

The examples described herein extend application lifecycle management (ALM) processes (e.g., create, update, delete, retrieve, import, export, uninstall, publish) to user-created application platform components. First and second components are generated within an application platform. The first component is customized at least by indicating whether the first component is subject to localization, defining a layering of the first component, and indicating whether the first component is protected from downstream modification. The second component is customized in accordance with customizing the first component, and is further customized by defining a dependency of the second component on the first component. The components are deployed in a target environment with metadata representing the customizations and enabling the ALM processes.