A processor-implemented method for transforming co-routines to equivalent sub-routines is provided. The method includes (i) receiving, an input from user for first language and first operating environment, and (ii) analyzing first language to transform co-routines of first language into sub-routines of second language by (a) determining at least one automatic variable for persistent variables and non-persistent variables across suspend cycles or resume cycles of co-routines, (b) transforming persistent variables and non-persistent variables into sub-routines of second language based on determined automatic variables, (c) determining return statements and yield statements in co-routines of first language for transforming the return statements and yield statements into sub-routines of the second language, and (d) translating the co-routines of first language into sub-routines of second language and second operating environment.

The embodiments of the present disclosure provide a method, an apparatus, a device and a medium for processing topological relation of tasks. The method includes: extracting at least one execution element from each of processing tasks based on a topological relation recognition rule; determining a dependency relation among the processing tasks according to content of the execution element of each processing task; and determining a topological relation among the processing tasks according to the dependency relation among the processing tasks.

An example embodiment may involve obtaining one or more blueprint files. The blueprint files may collectively define a system of processing nodes, a call flow involving a sequence of messages exchanged by the processing nodes, and message formats of the messages exchanged by the processing nodes. The example embodiment may also involve compiling the blueprint files into machine executable code. The machine executable code may be capable of: representing the processing nodes as decomposed, dynamically invoked units of logic, and transmitting the sequence of messages between the units of logic in accordance with the message formats. The units of logic may include a respective controller and one or more respective workers for each type of processing node.

A compiler system, computer-implemented method and computer program product for optimizing a program for multi-processor system execution. The compiler includes an interface component configured to load from a storage component program code to be executed by one or more processors (P1 to Pn) of a multi-processor system. The compiler further includes a static analysis component configured to determine data dependencies) within the program code, and further determines all basic blocks of the control flow graph providing potential insertion positions along paths where communication statements can be inserted to enable data flow between different processors at runtime. An evaluation function component of the compiler is configured to evaluate each potential insertion position with regards to its impact on program execution on the multi-processor system at runtime by using a predefined execution evaluation function.

Methods and systems are disclosed for accelerating big data operations by utilizing subgraph templates. In one example, a data processing system includes a data processing system comprising a hardware processor and a hardware accelerator coupled to the hardware processor. The hardware accelerator is configured with a compiler of an accelerator functionality to generate an execution plan, to generate computations for nodes including subgraphs in a distributed system for an application program based on the execution plan, and to execute a matching algorithm to determine similarities between the subgraphs and unique templates from an available library of templates.

Disclosed herein are system, method, and computer program product embodiments for self-paced migration of an application programming language (API) gateway. An embodiment operates by applying a policy chain comprising a first set of policies to an API request received at a first API gateway. The embodiment forwards the API request to a second API gateway and applies, at the second gateway, a virtual policy chain comprising a second set of policies to the API request. The embodiment then forwards the API request to the first API gateway and routes the API request to a corresponding backend API.

A method includes receiving source code of a program to be compiled and compiling the source code of the program. Compiling the source code includes identifying a first function in the source code of the program that is a candidate to be executed by a graphics processing unit (GPU), generating a first intermediate representation and a second intermediate representation for the first function, and inserting a second function in the program in place of the first function, wherein the second function is to select one of the first intermediate representation or the second intermediate representation to be executed. The method further includes providing a compiled program package including the second function, the first intermediate representation and the second intermediate representation.

Data are maintained in a distributed computing system that describe a graph. The graph represents relationships among items. The graph has a plurality of vertices that represent the items and a plurality of edges connecting the plurality of vertices. At least one vertex of the plurality of vertices includes a set of label values indicating the at least one vertex's strength of association with a label from a set of labels. The set of labels describe possible characteristics of an item represented by the at least one vertex. At least one edge of the plurality of edges includes a set of label weights for influencing label values that traverse the at least one edge. A label propagation algorithm is executed for a plurality of the vertices in the graph in parallel for a series of synchronized iterations to propagate labels through the graph.

With increasing demand for distributed intelligent physical systems performing big data analytics on the field and in real-time, processing-in-memory (PIM) architectures integrating 3D-stacked memory and logic layers could provide higher performance and energy efficiency. Towards this end, the PIM design requires principled and rigorous optimization strategies to identify interactions and manage data movement across different vaults.

A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.