Facilitating the implementation of cluster counters on lock value blocks in distributed file systems is provided herein. A system comprises a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations comprise receiving, from a first node device of a group of node devices, first information indicative of a first lock value block status of an object, and, from a second node device of the group of node devices, second information indicative of a second lock value block status of the object. The operations also can comprise merging the first information and the second information, resulting in a status of a lock value block of the object implemented at respective node devices of the group of node devices.

The invention relates to an apparatus for second offloads in a graphics processing unit (GPU). The apparatus includes an engine; and a compute unit (CU). The engine is arranged operably to store an operation table including entries. The CU is arranged operably to fetch computation codes including execution codes, and synchronization requests; execute each execution code; and send requests to the engine in accordance with the synchronization requests for instructing the engine to allow components inside or outside of the GPU to complete operations in accordance with the entries of the operation table.

The invention relates to a method for compiling code adapted for secondary offloads in a graphics processing unit (GPU). The method, performed by a processing unit, includes: reconstructing execution codes in a first kernel into a second kernel. The second kernel includes an operation table including entries, and computation codes. The computation codes include a portion of the execution codes, and synchronization hooks, and each synchronization hook includes information indicating one entry of the operation table. An order of the portion of the execution codes and the synchronization hooks in the computation codes matches an order of the execution codes in the first kernel, thereby enabling a compute unit (CU) in the GPU to execute the computation codes, and an engine in the GPU to instruct a component inside or outside of the GPU to complete a designated operation in accordance with content of each entry in the operation table.

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

The invention relates to a method for compiling code adapted for secondary offloads in a graphics processing unit (GPU). The method, performed by a processing unit, includes: reconstructing execution codes in a first kernel into a second kernel. The second kernel includes an operation table including entries, and computation codes. The computation codes include a portion of the execution codes, and synchronization hooks, and each synchronization hook includes information indicating one entry of the operation table. An order of the portion of the execution codes and the synchronization hooks in the computation codes matches an order of the execution codes in the first kernel, thereby enabling a compute unit (CU) in the GPU to execute the computation codes, and an engine in the GPU to instruct a component inside or outside of the GPU to complete a designated operation in accordance with content of each entry in the operation table.

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

A computer system for automated model integration of an information model with a corresponding application includes: an information model server for exposing an information model to a consumer, the exposed information model including model-elements for exposing types or classes, and for exposing instances of types or classes and their member-values; an application component for providing application code augmented with mapping descriptions defining how an internal information model of the application is mapped to the exposed information model; and a model integration component that: registers internal information model-elements to be exposed; maps the registered internal information model-elements to exposed information model-elements in accordance with the mapping descriptions; and updates an information model-element by: detecting a change of an internal or exposed information model-element; determining a synchronization direction; and performing match-making to determine a model-element corresponding to the changed model-element by using signatures of the corresponding information model-elements.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiling latency insensitive programs for a synchronous processor. One of the methods includes receiving an intermediate representation of a program specifying operations to be performed by a plurality of respective components of a synchronous processor, wherein the intermediate representation assigns, to each operation of the plurality of operations, a respective clock cycle value at which the operation is scheduled to be executed by the synchronous processor. The intermediate representation is processed to generate a respective update window for each operation in the intermediate representation requiring a hardware configuration update, wherein the update window specifies a time range during which a configuration update instruction can be executed to effectuate the hardware configuration update. Configuration update instructions are scheduled to occur during one or more update windows and according to the configuration constraints of the synchronous processor.

Embodiments relate to a system, program product, and method for implementing loop lock reservations, and, more specifically, for holding a lock reservation across some or all of the iterations of a loop, and under certain conditions, temporarily effect a running thread to yield the reservation and allow other threads to enter the lock.

A framework, method, and system for generating asynchronous code from state machines coded in a synchronous manner are described. The code is pre-processed into asynchronous code based on the framework prior to compilation thereof. The framework may include various structures and functions such as a save structure, a reentry function, a block wrapping function and a yield identification function.