Techniques for encrypting data using a key generated by a physical unclonable function (PUF) are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instruction and generate a decoded instruction. The decoded instruction includes operands and an opcode. The opcode indicates that execution circuitry is to encrypt data using a key generated by a PUF. The apparatus may further include execution circuitry to execute the decoded instruction according to the opcode to encrypt the data to generate encrypted data using the key generated by the PUF.

Systems and methods for defining mission profiles for a new engine are described. The method comprises selecting deployed engines from a set of existing engines based on components of the new engine using a first similarity metric; collecting field data associated with the deployed engines, the field data comprising usage and operating conditions for the deployed engines creating representative mission profiles from the field data using a second similarity metric; and defining the mission profiles for the new engine using the representative mission profiles.

A method for scheduling instructions for execution on a computer system includes scanning a plurality of loop instructions that are modulo scheduled to identify a first instruction and a second instruction that both utilize a register of the computer system upon execution of the plurality of instructions. The loop has a first initiation interval. The first instruction defines a first value of the register in a first iteration of the loop and the second instruction redefines the value of the register to a second value in a subsequent iteration of the loop prior to a use of the first value in the first iteration of the loop. A copy instruction is inserted in the loop instructions to copy the first value prior to execution of the second instruction. A schedule is determined after the insertion of the one or more copy instructions giving a second initiation interval.

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

A method for enhancing the security of a vehicle controller includes: performing, by a microcontroller, a secure boot when a vehicle controller is powered on and booted; determining, by the microcontroller, whether the secure boot is for a reprogramming mode or an other operation mode, among a plurality of operation modes of the vehicle controller, when the secure boot is completed; performing, by the microcontroller, a password input step, generating an error password, and automatically inputting the error password when the secure boot is for an operation mode other than the reprogramming mode from the plurality of operation modes of the vehicle controller; and jumping, by the microcontroller, to a main software (SW) routine immediately when the error password is inputted.

Disclosed is a hardware module with a 32-bit unit operation for processor supporting ARIA encryption and decryption, including: an instruction pipeline that executes an instruction fetch, instruction decoding, and an instruction execution; and an ARIA operation module that has a 32-bit unit operation system provided in the instruction execution pipeline to support ARIA encryption and decryption. Two types of instructions, ARIA substitution layer and diffusion layer instructions are provided as a 32-bit unit operation instruction in order to provide an ARIA encryption/decryption function through the ARIA operation module, the substitution layer instruction includes two instructions for an even round and an odd round of the ARIA encryption/decryption, and the diffusion layer includes four types of diffusion layer instructions for the even sub-round and four types of diffusion layer instructions for the odd sub-round.

This disclosure relates to methods and mechanisms for matrix computing which include machine embodiments with one or more matrix storage spaces for holding matrices and arrays for computing, where a matrix or an array is accessible by its columns, by its rows, or both, individually, or concurrently. A set of methods and mechanisms to build a large capacity instruction set with multi-length instructions to load, store, and compute with these matrices and arrays are also disclosed. Methods and access control mechanisms with keys to secure, share, lock and unlock regions in the storage space for matrices and arrays under the control of an operating system or a virtual machine hypervisor by permitted threads and processes are also disclosed. Methods and mechanisms to handle long immediate operands for use by shorter instructions using a payload instruction are also disclosed. The structure of the instructions with key instruction fields and a method for determining instruction length are also disclosed.

In general, the disclosure describes techniques for configuring a forwarding path of a network device. For example, a network device system includes a compiler. The compiler is configured to receive text comprising syntax elements in an arrangement that indicates a topology for a plurality of nodes. Additionally, the compiler is configured to generate, based on the text, code for instantiating the plurality of and compile the code to generate a software image. The network device system includes a network device comprising a forwarding manager configured to execute the software image to configure a forwarding path to include the corresponding forwarding path elements for each of the plurality of nodes. Additionally, the network device system includes at least one packet processor operably coupled to a memory, wherein the at least one packet processor is configured to process packets received by the forwarding unit by executing the forwarding path elements.

Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

An apparatus comprises processing circuitry to execute instructions, and decode circuitry to decode the instructions for execution by the processing circuitry. The decode circuitry is responsive to an authentication code generation instruction specifying a first source value to control the processing circuitry to generate an authentication code dependent on the first source value, and store the authentication code to a memory location associated with a store address formed using a value obtained from a register. By providing a single instruction, this reduces register pressure enabling improved performance by avoiding unnecessary load/store operations, and makes compilation of code using the authentication code generation instruction simpler. Because it does not store the result of the cryptographic function in the register bank, it also enables simple in-order CPU designs to hide the latency of slow cryptographic computations by allowing subsequent instructions to start executing before the cryptographic computation has completed.