In general, the disclosure describes techniques for configuring a forwarding path of a network device. For example, a network device system includes a compiler. The compiler is configured to receive text comprising syntax elements in an arrangement that indicates a topology for a plurality of nodes. Additionally, the compiler is configured to generate, based on the text, code for instantiating the plurality of and compile the code to generate a software image. The network device system includes a network device comprising a forwarding manager configured to execute the software image to configure a forwarding path to include the corresponding forwarding path elements for each of the plurality of nodes. Additionally, the network device system includes at least one packet processor operably coupled to a memory, wherein the at least one packet processor is configured to process packets received by the forwarding unit by executing the forwarding path elements.

A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

A processor has first, second and third ALUs. The first ALU has on a first side an input and an output. The second ALU has a first side facing the first side of the first ALU, an input and an output on the first side of the second ALU and being in a rotated orientation relative to the input and the output of the first side of the first ALU, and an output on a second side of the second ALU. The third ALU has a first side facing the second side of the second ALU, and an input and an output on the first side of the third ALU. The input of the first side of the first ALU is logically directly connected to the output of the first side of the second ALU.

A methodology for populating multiple instruction words is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first assigning a first instruction node to a first instruction word; identifying a dependent instruction node that is directly dependent upon a result of the first instruction node; first determining whether the dependent instruction node requires any input from two or more sources that are outside of a predefined physical range of each other, the range being smaller than the full extent of the data path; and second assigning, in response to satisfaction of at least one predetermined criteria including a negative result of the first determining, the dependent instruction node to the first instruction word.

In general, the disclosure describes techniques for configuring a forwarding path of a network device. For example, a network device system includes a compiler. The compiler is configured to receive text comprising syntax elements in an arrangement that indicates a topology for a plurality of nodes. Additionally, the compiler is configured to generate, based on the text, code for instantiating the plurality of and compile the code to generate a software image. The network device system includes a network device comprising a forwarding manager configured to execute the software image to configure a forwarding path to include the corresponding forwarding path elements for each of the plurality of nodes. Additionally, the network device system includes at least one packet processor operably coupled to a memory, wherein the at least one packet processor is configured to process packets received by the forwarding unit by executing the forwarding path elements.

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

Disclosed is a method and apparatus of operating a neural network. The neural network operation method includes receiving data for the neural network operation, verifying whether competition occurs between a first data traversal path corresponding to a first operation device and a second data traversal path corresponding to a second operation device, determining first operand data and second operand data from among the data using a result of the verifying and a priority between the first data traversal path and the second data traversal path, and performing the neural network operation based on the first operand data and the second operand data.

Disclosed is a hardware module with a 32-bit unit operation for processor supporting ARIA encryption and decryption, including: an instruction pipeline that executes an instruction fetch, instruction decoding, and an instruction execution; and an ARIA operation module that has a 32-bit unit operation system provided in the instruction execution pipeline to support ARIA encryption and decryption. Two types of instructions, ARIA substitution layer and diffusion layer instructions are provided as a 32-bit unit operation instruction in order to provide an ARIA encryption/decryption function through the ARIA operation module, the substitution layer instruction includes two instructions for an even round and an odd round of the ARIA encryption/decryption, and the diffusion layer includes four types of diffusion layer instructions for the even sub-round and four types of diffusion layer instructions for the odd sub-round.

Techniques for ratchet pointers in computing hardware are described. The technology includes a memory to store an object referenced by a ratchet pointer, and a processor to provide access to a slice of the object by decrypting a base address and a limit of the ratchet pointer, generating a cryptographic address in an encrypted format bound to an identity of the object and not the slice; and performing effective address generation for the cryptographic address based at least in part on the base address and the limit.