The invention relates to a work machine and a method for monitoring a control system at a work machine (1a). According to the method, in-parameters (32, 34, 36, 38) are obtained in the form of signals from the control system, wherein the control system generates actual values on one or more out-parameters (42, 44) in the form of signals based on said in-parameters. A characteristic of the invention is that a digital flow of data, comprising both said in-parameters and out-parameters via a control bus (5a, 5b), is addressed to a RAM buffer memory (3b,3c), which is included in a personal computer (3a) onboard the work machine, which buffer memory in FIFO mode writes a data file (id:1.1-id1:n) of a predetermined size, which is saved in a non-volatile data support memory (3d).

The present disclosure relates to a dataflow optimization method for low-power operation of a multicore system, the dataflow optimization method including: a step (a) of creating an FSM including a plurality of system states in consideration of dynamic factors that trigger a transition in system states for original dataflow; and a step (b) of optimizing the original dataflow through optimization of the created FSM.

A data flow graph-driven analytics platform is described in which highly-programmable data stream processing devices, referred to generally herein as data processing units (DPUs), operate to provide a scalable, fast and efficient analytics processing architecture. In general, the DPUs are specialized data-centric processors architected for efficiently applying data manipulation operations (e.g., regular expression operations to match patterns, filtering operations, data retrieval, compression/decompression and encryption/decryption) to streams of data units, such as packet flows having network packets, a set of storage packets being retrieved from or written to storage or other data units.

Apparatus comprises a processor to execute program instructions stored at respective memory addresses, processing of the program instructions being constrained by a prevailing capability defining at least access permissions to a set of one or more memory addresses; the processor comprising: control flow change handling circuitry to perform a control flow change operation, the control flow change operation defining a control flow change target address indicating the address of a program instruction for execution after the control flow change operation; and capability generating circuitry to determine, in dependence on the control flow change target address, an address at which capability access permissions data is stored; the capability generating circuitry being configured to retrieve the capability access permissions data and to generate a capability for use as a next prevailing capability in dependence upon at least the capability access permissions data.

Disclosed here are systems and methods that allow users, upon detecting errors within a running workflow, to either 1) pause the workflow and directly correct its design before resuming the workflow, or 2) pause the workflow, correct the erred action within the workflow, resume running the workflow, and afterwards apply the corrections to the design of the workflow. The disclosure comprises functionality that pauses a single workflow and other relevant workflows as soon as the error is detected and while it is corrected. The disclosed systems and methods improve communication technology between the networks and servers of separate parties relevant and/or dependent on successful execution of other workflows.

Techniques for performing an upgrade can include: defining integration points each associated with a workflow processing point included in an upgrade workflow; receiving command lists each include commands of an integration point; associating each command of a command list with a code entity; performing processing that performs an upgrade workflow to upgrade a system, wherein the processing includes: executing code corresponding to the upgrade workflow, wherein a workflow processing point of the workflow is associated with a first integration point; and in response to said executing reaching the workflow processing point corresponding to the first integration point, performing second processing including: executing commands of a command list associated with the first integration point; and for each command executed, invoking a corresponding code entity that performs customized processing in connection with upgrading a first feature, facility or service in the system.

Implementations generally relate to management of metadata groups and associated workflows. In some implementations, a method includes receiving a workflow request, wherein the workflow request includes information associated with a metadata group. The method further includes providing a workflow list of available workflows based on the metadata group. The method further includes receiving a selection of a workflow from the workflow list. The method further includes providing the workflow and a form associated with the workflow.

Provided is a processor that is used for limited purposes such as preprocessing of raw data and that has a small circuit scale and high program processing efficiency, wherein an instruction block includes a 2-bit opcode. The processor can move to a branch destination or perform an operation by using an immediate bit accompanying the instruction block, by assigning a branch flag or an immediate instruction determination bit corresponding to the opcode.

A primary check system includes: a control unit configured to output data for primary check to a plurality of primary check circuits as a serial signal via a serial communication line; and a serial and parallel conversion circuit configured to convert the data for primary check, that is received as the serial signal, into a parallel signal and transmit the parallel signal to the plurality of primary check circuits, and the control unit is configured to set the serial and parallel conversion circuit into an active state before a primary check is started, and set the serial and parallel conversion circuit into an inactive state when the primary check is completed.

A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. A first tile in a first node can include a processor with a processor output and a first register network configured to receive information from the processor output and information from one or more of the multiple other tiles in the first node. In response to an output instruction and a delay instruction, the register network can provide an output signal to one of the multiple other tiles in the first node. Based on the output instruction, the output signal can include one or the other of the information from the processor output and the information from one or more of the multiple other tiles in the first node. A timing characteristic of the output signal can depend on the delay instruction.