A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.

Examples include an example computing system comprising a first storage to store executable code, wherein the executable code comprises a plurality of instructions, a second storage to store a first parameter of the executable code, a processing unit to execute each of the instructions of the code, and a monitoring component to, upon execution of each of the instructions of the code by the processing unit, update a second parameter of the code based on that instruction, wherein the monitoring component is to compare the first parameter and the second parameter, and to control execution of further executable code by the processing unit based on the comparison.

A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

A method comprises receiving a current instruction for metadata processing performed in a metadata processing domain that is isolated from a code execution domain including the current instruction. The method further comprises determining, by the metadata processing domain in connection with metadata for the current instruction, whether to allow execution of the current instruction in accordance with a set of one or more policies. The one or more policies may include a set of rules that enforces execution of a complete sequence of instructions in a specified order from a first instruction of the complete sequence to a last instruction of the complete sequence. The metadata processing may be implemented by a metadata processing hierarchy comprising a control module, a masking module, a hash module, a rule cache lookup module, and/or an output tag module.

Systems and methods are provided for generating an event type and extending event message streaming. The generating an event type includes receiving event definition data. The disclosed technology includes an event type generator that generates scripts in a variety of languages for processing an event of the event type and event dictionary data including event schema associated with the event type. The event dictionary data represents a lightweight library package for merging into a micro service. The event type generator further registers the event type in an event message streamer thereby extending the event message streaming with the event type. The event message streamer provides an event bus that receives an event of the registered event type from a micro service for publishing. The event message streamer delivers the event in an event message to one or more micro services that subscribes to the event type for consuming.

A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for execution of a conditional statement by an arithmetic and/or bitwise unit. A computer program that comprises a conditional statement that comprises a Boolean condition is accessed. The Boolean condition is transformed into an arithmetic and/or bitwise expression of the Boolean condition. An arithmetic and/or bitwise expression of the computer program comprises the arithmetic and/or bitwise expression of the Boolean condition in place of the Boolean condition. The arithmetic and/or bitwise expression of the computer program is executed by an arithmetic and/or bitwise operation unit of a processor.

A method for supporting throughput-oriented computing includes a single instruction multiple threads (SIMT) program configured to launch a plurality of warps, each respective warp of the plurality of warps comprises threads to be executed in lockstep within the each respective warp. Individual warp sizes of the plurality of warps are used as a runtime parameter for the SIMT program, such that a parameterized SIMT program is provided, which is parameterizable via the individual warp sizes, and the parameterized SIMT program is executed on a single instruction multiple data (SIMD) vector architecture.

In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.