A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

A method of score prediction uses hierarchical attention. Word features, positioning features, participant embedding features, and metadata are extracted from a transcript of a conversation. A word encoder vector is formed by multiplying weights of a word encoder layer to one or more word features. A sentence vector is formed by multiplying weights of a word attention layer to word encoder vectors. An utterance encoder vector is formed by multiplying weights of an utterance encoder layer to the sentence vector. A conversation vector is formed by multiplying weights of an utterance attention layer to utterance encoder vectors. The utterance encoder vector is combined with one or more positioning features and one or more participant embedding features. A predicted net promoter score is generated by multiplying weights of an output layer to the conversation vector combined with the metadata. The predicted net promoter score is presented in a list of conversations.

A processor includes a front end to receive an encrypted instruction sequence. The processor also includes a decoder including logic to identify a encrypted command from a packet in the encrypted instruction sequence, logic to identify a key index from the packet, logic to determine an encrypted opcode lookup table with the key index, logic to look up a decoded opcode from the encrypted opcode lookup table based upon the key index, and logic to forward the decoded opcode for execution.

An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.

Our machine architecture and machine procedures use robustness, unpredictably and variability to hinder malware infection. In some embodiments, our machine instruction opcodes are randomized. The computing behavior of our machine is structurally stable (invariant) to small changes made to its machine instructions. Our invention expands the engineering method of stability to a cryptographically stable machine that is resistant to malware sabotage by an adversary. Our procedures use quantum randomness to build unpredictable stable instructions. Our machine procedures can execute just before running a program so that the computing task can be performed with a different representation of its instructions during each run. A process of hiding a key or data inside of random noise is described that protects the privacy of the machine instruction opcodes and operands. In some embodiments, quantum randomness generates random noise, using photonic emission with a light emitting diode.

A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.

A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16) of the processing element, and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.

Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.