A processor comprises at least one delay stage for each processing circuit and switching circuitry for selectively switching the delay stage into or out of a communication path involved in message exchange. For processing circuits up to a defective processing circuit in the column, the delay stage is switched into the communication path, and for processing circuits above the defective processing circuit in the column, including a repairing processing circuit which repairs the defective processing circuit the delay stage is switched out of the communication path whereby the fixed transmission time of processing circuits is preserved in the event of a repair of the column.

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

Data integrity logic is executable by a processor to generate a data integrity code using a hardware-based secret. A container manager, executable by the processor, creates a secured container including report generation logic that determines measurements of the secured container, generates a report according to a defined report format, and sends a quote request including the report. The defined report format includes a field to include the measurements and a field to include the data integrity code, and the report format is compatible for consumption by any one of a plurality of different quote creator types.

A micro-processor circuit and a method of performing neural network operation are provided. The micro-processor circuit is suitable for performing neural network operation. The micro-processor circuit includes a parameter generation module, a compute module and a truncation logic. The parameter generation module receives in parallel a plurality of input parameters and a plurality of weight parameters of the neural network operation. The parameter generation module generates in parallel a plurality of sub-output parameters according to the input parameters and the weight parameters. The compute module receives in parallel the sub-output parameters. The compute module sums the sub-output parameters to generate a summed parameter. The truncation logic receives the summed parameter. The truncation logic performs a truncation operation based on the summed parameter to generate a plurality of output parameters of the neural network operation.

The invention discloses a method and a device for constructing a SQL statement based on reinforcement learning, wherein the method includes: initializing an actor-critic network parameter; acquiring a sequence pair of natural language and real SQL statement from a data set; inputting a natural language sequence into an actor network encoder, and inputting a real SQL sequence into a critic network encoder; using an encoded hidden state as an initialized hidden state of a corresponding decoder; gradually predicting, by an actor network decoder, a SQL statement action, and inputting the SQL statement action to a critic network decoder and an environment to obtain a corresponding reward; and using a gradient descent algorithm to update the network parameters, and obtaining a constructing model of the natural language to the SQL statement after repeated iteration training.

Techniques for comparing BF16 data elements are described. An exemplary BF16 comparison instruction includes fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand, wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a data element at that position, and update a flags register based on the comparison.

Provided is a processor that is used for limited purposes such as preprocessing of raw data and that has a small circuit scale and high program processing efficiency, wherein an instruction block includes a 2-bit opcode. The processor can move to a branch destination or perform an operation by using an immediate bit accompanying the instruction block, by assigning a branch flag or an immediate instruction determination bit corresponding to the opcode.

Techniques for performing square root or reciprocal square root calculations on BF16 data elements in response to an instruction are described. An example of an instruction is one that includes fields for an opcode, an identification of a location of a packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, a calculation of a square root value of a BF16 data element in that position and store a result of each square root into a corresponding data element position of the packed data destination operand.

Provided are systems and methods for big data processing and related architectures. Various embodiments include a configurable load store unit, a computational register file, and related methods, systems, and devices. Requests to utilize at least one of a memory and a storage can be received at a computing system comprising a local memory and local storage. Systems and methods can determine availability of a remote memory and a remote storage at one or more remote nodes accessible by the computing system, determine a distribution among the local memory, local storage, and one or more remote nodes to fulfill the request, and based on the determination, utilize at least one of: a memory associated with a first set of one or more remote nodes via a first interconnect, and a storage associated with a second set of one or more remote nodes via a second interconnect.

Systems, apparatuses, and methods for implementing a family of lossy sparse load single instruction, multiple data (SIMD) instructions are disclosed. A lossy sparse load unit (LSLU) loads a plurality of values from one or more input vector operands and determines how many non-zero values are included in one or more input vector operands of a given instruction. If the one or more input vector operands have less than a threshold number of non-zero values, then the LSLU causes an instruction for processing the one or more input vector operands to be skipped. In this case, the processing of the instruction of the one or more input vector operands is deemed to be redundant. If the one or more input vector operands have greater than or equal to the threshold number of non-zero values, then the LSLU causes an instruction for processing the input vector operand(s) to be executed.