Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.

Provided is a system and method for executing an encrypted software program within a host platform. The execution may be bifurcated among a trusted module and an untrusted area of the host platform. In one example, the method may include receiving bytecode and encrypted data of a software program, decrypting, via a secure memory area, the encrypted data into decrypted data, executing, via the secure memory area, instructions from the bytecode on the decrypted data to generate execution results, encrypting the generated execution results, and transmitting the encrypted execution results to a remote computing device.

An apparatus and method for supporting deprecated instructions. For example, one embodiment of a processor comprises: A processor comprising: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; at least one core of the plurality of cores comprising: a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine, wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support.

An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. An embodiment of a processor includes: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

The technology disclosed herein pertains to a system and method for providing optimization of embedded computation instruction set (CIS), the method including downloading the CIS to a computational storage device (CSD), committing the CIS to a program slot in a computational storage processor of the CSD, simulating execution of the CIS at the committed slot to generate static analysis of one or more registers of the CIS to determine ranges of values that the one or more registers can take through a lifecycle of the CIS, demoting one or more of the registers to lower size registers, and generating a native instruction set from the CIS based on the register demotions.

A process includes receiving a table data set that represents mappings between a plurality of operand patterns indicating types of operands possibly included in a first instruction used in a first assembly language and a plurality of second instructions used in a second assembly language or a machine language corresponding to the second assembly language. The table data set maps two or more of the second instructions to each of the operand patterns. The process also includes generating, based on the table data set, a translation program used to translate first code written in the first assembly language into second code written in the second assembly language or the machine language. The translation program defines a process of determining an operand pattern of an instruction included in the first code and outputting two or more instructions of the second code according to the determined operand pattern.

A method for executing new instructions includes the following steps: receiving an instruction and determining whether the received instruction is a new instruction. When the received instruction is the new instruction, entering a system management mode, and simulating the execution of the received instruction by executing at least one old instruction in the system management mode.

A method for executing new instructions includes the following steps. An instruction is received. A determination is made as to whether the received instruction is a new instruction. When the received instruction is the new instruction, a emulation flag is generated. The emulation flag is a first value. A system management interrupt is generated according to the emulation flag. In response to the system management interrupt, entering the system management mode and simulating the execution of the received instruction in the system management mode to generate a simulation execution result. The simulation execution result is stored in a system management memory.

A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, the processor executes the following steps through a conversion program: determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction; and simulating the execution of the received instruction by executing the at least one old instruction.