Techniques are provided for implementing a distributed control plane to facilitate communication between a container orchestration platform and a distributed storage architecture. The distributed storage architecture hosts worker nodes that manage distributed storage that can be made accessible to applications within the container orchestration platform through the distributed control plane. However, the worker nodes may support an imperative model of program commands, but the container orchestration platform and applications therein utilize a declarative model of programming commands not supported by the distributed storage architecture. Accordingly, the distributed control plane is configured with control plane controllers that are paired with the worker nodes and are configured to reformat commands between the imperative model and the declarative model. In this way, the control plane controllers can facilitate communication and performance of commands between the applications of the container orchestration platform and the worker nodes of the distributed storage architecture.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

An instruction conversion device, an instruction conversion method, an instruction conversion system, and a processor are provided. The instruction conversion device includes a monitor for determining whether a ready-for-execution instruction is an instruction that belongs to a new instruction set or an extended instruction set, wherein the new instruction set and the extended instruction set have the same type of the instruction set architecture as that of the processor. If the ready-for-execution instruction is determined as an extended instruction, this extended instruction is converted into a converted instruction sequence by means of the conversion system, this converted instruction sequence is then sent to the processor for executions, thereby extending the lifespans of the electronic devices embodied with old-version processors.

A method for executing new instructions includes the following steps: receiving an instruction and determining whether the received instruction is a new instruction. When the received instruction is the new instruction, entering a system management mode, and simulating the execution of the received instruction by executing at least one old instruction in the system management mode.

A recording medium stores a program for causing a computer to execute a process including: converting, in a first source code corresponding to a first-type processor, a first load command for a first mask register included in the first-type processor into a second load command for a second mask register included in a second-type processor; and converting, when a first SIMD command for performing an arithmetic operation using the first mask register exists after the first load command in the first source code and a state of a value of the first mask register does not coincide with a state of a value of the first mask register, the first SIMD command into a second SIMD command corresponding to the second-type processor and a change command for changing a state of a value of the second mask register to a state of a value of the second mask register.

An instruction simulation device and a method thereof are provided. The simulation device includes a monitor, which is configured to determine whether a ready-for-execution instruction is an instruction under a new/extended instruction set sharing the same instruction set architecture as that of the processor. If the ready-for-execution instruction is an extended instruction, it is converted into a simulation program which consists of a compatible instruction sequence further composed of at least one native instruction of the processor or a compatible instruction recognizable/executable by the processor. An execution result of the extended instruction is simulated by executing the simulation program, thereby extending the service life of an electronic appliance embodied with the disclosed simulation device therein.

Methods, system and computer program product, the method comprising: from high level language code (HLLC), receiving a request for reading a data set from a tape onto an object storage connected over TCP/IP to a mainframe; from the HLLC, allocating a data set on a tape comprising information to be imported, the allocation being in a format of the stored data set record and associated with a JFCB, the tape is mounted in SL mode; updating the JFCB to BLP mode; reading from the tape VOL1 data, and for each stored file initiating by the HLLC: reading HDR1/2, content block-by-block; EOF1/2 of the file; organizing the VOL1, HDR1, HDR2, content, EOF1 and EOF2 in the object storage; and closing the tape, wherein said reading is performed without setting a JES of the mainframe to BLP mode, and said reading is performed without unmounting the tape after each file.

A new device executing an application on a new central processing unit (CPU), determines whether the application is for a legacy device having a legacy CPU. When the new device determines that the application is for the legacy device, it executes the application on the new CPU with selected available resources of the new device restricted to approximate or match a processing behavior of the legacy CPU, e.g., by reducing a usable portion of a return address stack of the new CPU and thereby reducing a number of calls and associated returns that can be tracked

Methods, system and computer program product, the method comprising: from high level language code (HLLC), receiving a request for reading a data set from a tape onto an object storage connected over TCP/IP to a mainframe; from the HLLC, allocating a data set on a tape comprising information to be imported, the allocation being in a format of the stored data set record and associated with a JFCB, the tape is mounted in SL mode; updating the JFCB to BLP mode; reading from the tape VOL1 data, and for each stored file initiating by the HLLC: reading HDR1/2, content block-by-block; EOF1/2 of the file; organizing the VOL1, HDR1, HDR2, content, EOF1 and EOF2 in the object storage; and closing the tape, wherein said reading is performed without setting a JES of the mainframe to BLP mode, and said reading is performed without unmounting the tape after each file.