An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

Described herein are systems and methods for microarchitectural sensitive tag flow. For example, some methods include detecting dependence of data stored in a second data storage circuitry on the first instruction, where the first instruction will output a value to be stored in the second data storage circuitry, and wherein the second data storage circuitry is associated with a third tag indicating whether the second data storage circuitry has been designated as storing sensitive data; responsive to the dependence of data stored in the second data storage circuitry on the first instruction, checking whether the second tag indicates a sensitive instruction; and, responsive to the second tag indicating a sensitive instruction, updating the third tag to indicate that data stored in the second data storage circuitry has been designated as sensitive.

According to one aspect, a computer-implemented method for thread context preservation in a configuration including a core configurable between a single thread (ST) mode and a multithreading (MT) mode is provided. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. Based on determining, by the core in the MT mode, that MT is to be disabled, switching from the MT mode to the ST mode is performed, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context including program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed.

A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.

A data storage apparatus, memory controller, and or method operation method may be disclosed. The memory controller may include an address generator configured to generate an operation target address and a destination address. The memory controller may be configured to output the operation target address and the destination address. The memory controller may include a data processor configured to receive the operation target address, read data by accessing the corresponding address of the operation target address, perform an operation on the read data, access the destination address, and write a result of the operation in the accessed destination address.

A processor and an instruction scheduling method for X-channel interleaved multi-threading, where X is an integer greater than one. The processor includes a decoding unit and a processing unit. The decoding unit is configured to obtain one instruction from each of Z predefined threads in each cyclic period, decode the Z obtained instructions to obtain Z decoding results, and send the Z decoding results to the processing unit, where each cyclic period includes X sending periods, one decoding result is sent to the processing unit in each sending period, a decoding result of the Z decoding results may be repeatedly sent by the decoding unit in a plurality of sending periods, wherein 1≤Z<X or Z=X, and wherein Z is an integer. The processing unit (32) is configured to execute the instruction based on the decoding result.

A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register field) executes, the queue is searched for any entries that contain instructions that depend upon the executed write instruction. Each such entry stores the value of the register field at the time the instruction in the entry was processed. If such an entry is found in the queue and its stored value of the register field does not match the value that the write instruction wrote to the register field, then the processor flushes the pipeline and restarts at a state so as to correctly execute the instruction.

A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.

A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the “control” register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.