In one embodiment, a microprocessor, comprising: first logic configured to dynamically adjust a maximum prefetch count based on a total count of predicted taken branches over a predetermined quantity of cache lines; and second logic configured to prefetch instructions based on the adjusted maximum prefetch count.

The embodiments disclosed herein relate to predictive rate limiting. A workload for completing a request is predicted based on, for example, characteristics of a ruleset to be applied and characteristics of a target set upon which the ruleset is to be applied. The workload is mapped to a set of tokens or credits. If a requestor has sufficient tokens to cover the workload for the request, the request is processed. The request may be processed in accordance with a set of processing queues. Each processing queue is associated with a maximum per-tenant workload. A request may be added to a processing queue as long as adding the request does not result in exceeding the maximum per-tenant workload. Requests within a processing queue may be processed in a First In First Out (FIFO) order.

An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information. The instruction processing apparatus selectively enables an access channel of the instruction cache based on the path prediction information by using the access control unit, to reduce dynamic power consumption in access. A corresponding path prediction method, a computer system, and a system-on-chip are also disclosed.

An example method of generating an execution profile of a firmware module comprises: receiving an execution trace of a firmware module comprising a plurality of executable instructions, wherein the execution trace comprises a plurality of execution trace records, wherein each execution trace record of the plurality of execution trace records indicates a successful execution of an executable instruction identified by a program counter (PC) value; retrieving a first execution trace record of the plurality of execution trace records, wherein the first execution trace record comprises a first PC value; identifying a first executable instruction referenced by the first PC value; identifying a firmware function containing the first executable instruction; incrementing a cycle count for the firmware function by a number of cycles associated with the first executable instruction; and generating, using the cycle count, an execution profile of the firmware module.

A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching instructions if the resources are available based on data stored in the time-resource matrix, and wherein execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline.

A method comprising responsive to a first instruction requesting a memory heap operation, identifying a data block of a memory heap; accessing a tag history for the data block, the tag history comprising a plurality of tags previously assigned to the data block; assigning a tag to the data block, wherein assigning the tag comprises verification that the tag does not match any of the plurality of tags of the tag history; and providing the assigned tag and a reference to a location of the data block.

A system and method for mitigating micro-architectural replay attacks in a processing system by delaying speculative execution on the processing system of a set of processor instructions upon detection that the set of processor instructions are part of a micro-architectural replay attack by detecting repeating speculative execution of the set of processor instructions interleaved with misspeculation and squashing of the set of processor instructions.

A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.

The technology disclosed herein pertains to a system and method for profiling performance of an embedded computation instruction set (CIS), the method including receiving a profiling component to a computational storage device (CSD), the profiling component being configured to measure one or more execution parameters of a computational instruction set (CIS), executing the CIS at a program slot in a computational storage processor of the CSD, monitoring the execution of the CIS to generate a log of the execution parameters of the CIS, and communicating the log to a host in response to receiving a get-log page command.

Memory systems and memory control methods are described. According to one aspect, a memory system includes a plurality of memory cells individually configured to store data, program memory configured to store a plurality of first executable instructions which are ordered according to a first instruction sequence and a plurality of second executable instructions which are ordered according to a second instruction sequence, substitution circuitry configured to replace one of the first executable instructions with a substitute executable instruction, and a control unit configured to execute the first and second executable instructions to control reading and writing of the data with respect to the memory, wherein the control unit is configured to execute the first executable instructions according to the first instruction sequence, to execute the substitute executable instruction after the execution of the first executable instructions, and to execute the second executable instructions according to the second instruction sequence as a result of execution of the substitute executable instruction.