The present disclosure relates to a computing device. A computing device includes an arithmetic processing circuit configured to execute a program, and a program memory for storing the program. Each instruction in the program has a length of 16 bits. The program memory has a first memory area, and a second memory area in which higher addresses than the first memory area are associated. The arithmetic processing circuit has a 16-bit program counter for specifying an address to be read, and reads and executes an instruction at an address corresponding to an upper 15-bit value of the program counter from a target memory area, wherein the target memory area is, of the first memory area and the second memory area, a memory area corresponding to a value of a least significant bit in the program counter.

A computer processor that implements pre-translation of virtual addresses with target registers is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual instruction address, the virtual instruction address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.

A processor employs hardware to save the program counter value of the next instruction to be executed in a branch instruction when an exception occurs. This is the branch target address in the case where the exception occurs in the delay slot of a taken branch. The value is saved to a register when an exception occurs. The kernel code can then read the register to determine the address which it should return to after an exception. This eliminates the need to emulate the branch instruction and also eliminates the need to keep the kernel up to date with the knowledge of how to emulate all branches in an Instruction Set Architecture.

Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

Method for detecting the linear extraction of information in a processor using an instruction register for storing an instruction includes an operation code. The method includes monitoring the instructions successively stored in the instruction register including decoding the operation codes, determining the number of consecutive operation codes encoding incremental branches, and generating a detection signal if the number is greater than or equal to a detection threshold.

A secure processor, comprising a logic execution unit configured to process data based on instructions; a communication interface unit, configured to transfer of the instructions and the data, and metadata tags accompanying respective instructions and data; a metadata processing unit, configured to enforce specific restrictions with respect to at least execution of instructions, access to resources, and manipulation of data, selectively dependent on the received metadata tags; and a control transfer processing unit, configured to validate a branch instruction execution and an entry point instruction of each control transfer, selectively dependent on the respective metadata tags.

This document discloses aspects of function call authorization for program flow control. In some aspects, a processor encounters a first instruction to initiate or call a function. The processor compares an immediate value of a second instruction at an entry point of the function to a function call authorization value stored in a register. In response to the immediate value of the second instruction matching the function call authorization value stored in the register the process transfers control flow to the function. Alternatively, if the values do not match, an exception or fault may be raised to halt execution of the function or other code. By so doing, these and other aspects of function call authorization may prevent fault injection attacks, execution of unauthorized instructions, or access to sensitive data.

A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.

Load dependent branch prediction is described. In accordance with described techniques, a load dependent branch instruction is detected by identifying that a destination location of a load instruction is used in an operation for determining whether a conditional branch is taken or not taken. The load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction is injected in an instruction stream of a processor for fetching data of a future load instruction using an address of the load instruction offset by a distance based on the step size. An additional instruction is injected in the instruction stream of the processor for precomputing an outcome of a load dependent branch using an address computed based on an address of the operation and the data of the future load instruction.