An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p−q−e bits of the lower limit and the upper limit is derivable from the most significant p−q−e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2.sup.x regions of size 2.sup.n1, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.

Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.

A method and apparatus are disclosed to perform the circular addressing to emulate a virtually unlimited memory space despite the fixed capacity of a physical memory by readdressing the portion of the data that exceeds the pre-defined length of the circular addressing region to another pre-defined address in the circular addressing region. Data segments in a data sample can be loaded and computed with recalculated circular addresses for different applications.

Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.

Managing the capture of information. A plurality of instruction units of an instruction stream are received in parallel by a plurality of instruction decode units of a processor. One instruction decode unit of the plurality of instruction decode units receives a prefix instruction and another instruction decode unit of the plurality of instruction decode units receives a prefixed instruction. The prefixed instruction is an instruction to be modified by the prefix instruction. Information associated with processing of the plurality of instruction units is captured, and the capturing includes modifying the information to be captured to manage the prefix instruction and the prefixed instruction separately received by the instruction decode units as a single instruction.

The problem to be solved is to seek an alternative to known addressing methods which provides the same or similar effects or is more secure. Solution The problem is solved by a method (40) of addressing memory in a data-processing apparatus (10) comprising, when a central processing unit (11), while performing a task (31, 32, 33, 34) of the apparatus (10), executes an instruction involving a pointer (59) into a segment (s, r, d, h, f, o, i, c) of the memory: decoding the instruction by means of an instruction decoder (12), generating a virtual address (45) within the memory by means of a safe pointer operator (41) operating on the pointer (59), augmenting the virtual address (45) by an identifier (43) of the task (31, 32, 33, 34) and an identifier (44) of the segment (s, r, d, h, f, o, i, c), said identifiers (43, 44) being hardware-controlled (42), and, based on the augmented address (45), dereferencing the pointer (59) via a memory management unit (13).

A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.

Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

In one embodiment, an apparatus includes an input/output virtualization (IOV) device comprising: at least one function circuit to be shared by a plurality of virtual machines (VMs); and a plurality of assignable device interfaces (ADIs) coupled to the at least one function circuit, wherein each of the plurality of ADIs is to be associated with one of the plurality of VMs and comprises a first process address space identifier (PASID) field to store a first PASID to identify a descriptor queue stored in a host address space and a second PASID field to store a second PASID to identify a data buffer located in a VM address space. Other embodiments are described and claimed.

Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.