A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.

A method and apparatus are disclosed to perform the circular addressing to emulate a virtually unlimited memory space despite the fixed capacity of a physical memory by readdressing the portion of the data that exceeds the pre-defined length of the circular addressing region to another pre-defined address in the circular addressing region. Data segments in a data sample can be loaded and computed with recalculated circular addresses for different applications.

This patent application describes a device (for example, a microprocessor) in which an additional channel for exchanging useful information is implemented.

Such device may extract additional useful information (for example, information that serves to access other address spaces, control caching, prefetching, synchronization, or speculative execution) from logical addresses that are called by executable operations, and also obtains additional useful information using prefixes, suffixes, or the context of the executable operation.

In other words, this invention describes the use of logical addresses, prefixes and/or suffixes of executable operations, including in aggregate with the context, as an additional channel for exchanging useful information with a computer device. As well as the set of solutions, that use this information.

In addition, this method allows the simultaneous addressing of different address spaces without reloading supplementary or system registers and/or allows the use of additional useful information to control the address translation process or the memory accessing (control transfer) process.

This invention also describes devices that support access to other address spaces using ordinary pointers (without switching context), that use parameterized prefixes or suffixes to transmit additional information during the execution of operations, and conversely, that automatically modify the code executed by them, and that use a different number of bits in a logical address to represent different identifiers of address spaces (contexts) and a new scheme for coding immediate values (for example, offsets).

These are distinct ideas, but they are inspired by the idea of an additional channel and are used in the implementations described in this patent application, therefore they are included in this application.

In particular, such device may simultaneously (that is, without needing to regularly switch its mode of operation) use both logical (for example, those that are linear, or address virtual memory), and lower level (for example, physical) addresses in general purpose commands.

The device in which in which an additional channel for exchanging useful information is implemented, may also use several different rules to translate high level addresses into lower level addresses, thereby dispensing with switching the device's mode of operation in order to use different rules to translate addresses in neighboring commands or in compact fragments of the program code.

Managing exception handling. A plurality of instruction units of an instruction stream are selected to be decoded in parallel by a plurality of instruction decode units of a processor. The plurality of instruction units includes a prefix instruction and a prefixed instruction. The prefixed instruction is an instruction to be modified by the prefix instruction. An exception condition associated with the prefixed instruction is determined. Exception handling is performed for the prefixed instruction, in which the performing includes determining an address at which to restart execution of the instruction stream. The determining the address includes adjusting the address at which to restart execution based on the prefix instruction to be separately decoded by an instruction decode unit.

Managing exception handling. A plurality of instruction units of an instruction stream are selected to be decoded in parallel by a plurality of instruction decode units of a processor. The plurality of instruction units includes a prefix instruction and a prefixed instruction. The prefixed instruction is an instruction to be modified by the prefix instruction. An exception condition associated with the prefixed instruction is determined. Exception handling is performed for the prefixed instruction, in which the performing includes determining an address at which to restart execution of the instruction stream. The determining the address includes adjusting the address at which to restart execution based on the prefix instruction to be separately decoded by an instruction decode unit.

A short pointer mode application is loaded in an address space configured for use by a plurality of types of applications including the short pointer mode application and a long pointer mode application. The address space has a first portion addressable by short pointers of a defined size and a second portion addressable by long pointers of another defined size. The other defined size is different from the defined size. Based on executing the short pointer mode application, one or more short pointers of the short pointer mode application are converted to one or more long pointers; and the one or more long pointers are used to access memory within the first portion of the address space addressable by short pointers.

A computer-implemented method for transforming implicit data structures expressed by assembler code into high-level language structures includes analyzing a section of assembler code to identify a plurality of data items. The computer-implemented method further includes storing the plurality of data items in a plurality of groups. The computer-implemented method further includes modifying one or more groups in the plurality of groups based, at least in part, on a pair of adjacent groups having a non-identical overlap. The computer-implemented method further includes creating an overlap list for each group. The computer-implemented method further includes generating data modeling language for the section based, at least in part, on each overlap list. A corresponding computer system and computer program product are also disclosed.

Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.

An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.