A processor includes: a storage unit that stores instructions; a counting unit that specifies an instruction to be decoded by a count value; a decoding unit that decodes an instruction; and a control unit that, when the decoded instruction is a repeat instruction, updates the count value of the counting unit so as to cause repeat target instructions in number corresponding to a designated number of instructions, out of instructions succeeding the repeat instruction, to be repeatedly executed a designated number of repetition times, and generates updated operands being operation objects of the repeat target instructions that are to be executed for the second or later time, and when the repeat target instructions are to be executed for the second or later time, updates operands of the repeat target instructions for use in the second or later time execution, to the generated updated operands and outputs the updated operands.

A device for contactless communication with a terminal, comprising: an antenna for communication with the terminal; an embedded chip configured to communicate with the terminal in accordance with a contactless transmission protocol whereby a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip to maintain a connection with the terminal, the embedded chip being configured to communicate requests to the terminal to extend the waiting time for response; and a module configured to perform processing formed of a plurality of discrete operations, the module being configured to, in response to completing a subset of one or more discrete operations within a waiting time interval set by the terminal, send a first type of command to the embedded chip if the processing is not complete; wherein the embedded chip is further configured to, in response to receiving the first type of command, communicate a request to the terminal to extend the waiting time for response.

A device for contactless communication with a terminal, comprising: an antenna for communication with the terminal; an embedded chip configured to communicate with the terminal in accordance with a contactless transmission protocol whereby a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip to maintain a connection with the terminal, the embedded chip being configured to communicate requests to the terminal to extend the waiting time for response; and a module configured to perform processing formed of a plurality of discrete operations, the module being configured to, in response to completing a subset of one or more discrete operations within a waiting time interval set by the terminal, send a first type of command to the embedded chip if the processing is not complete; wherein the embedded chip is further configured to, in response to receiving the first type of command, communicate a request to the terminal to extend the waiting time for response.

In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By utilizing the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.

An example operation may include one or more of executing a waiting period of time within a software application being accessed by a user, executing an animation via the software application during the waiting period, determining a result of the software application being accessed by the user, determining additional time to add to the waiting period of time based on the result, via the software application, executing the waiting period with the additional time, augmenting the animation based on the additional time to add to the waiting period, via the software application, and executing the augmented animation via the software application during the additional time. At least one portion of the example operation: integrates with an artificial intelligence (AI) chatbot, interacts with the AI chatbot, is performed by the AI chatbot, and/or is associated with an AI model.

An example operation may include one or more of executing a waiting period of time within a software application being accessed by a user, executing an animation via the software application during the waiting period, determining a result of the software application being accessed by the user, determining additional time to add to the waiting period of time based on the result, via the software application, executing the waiting period with the additional time, augmenting the animation based on the additional time to add to the waiting period, via the software application, and executing the augmented animation via the software application during the additional time. At least one portion of the example operation: integrates with an artificial intelligence (AI) chatbot, interacts with the AI chatbot, is performed by the AI chatbot, and/or is associated with an AI model.

Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.

Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.

This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.