In one embodiment, a processor includes: a decode circuit to decode a branch instruction, the branch instruction comprising a hint field to provide spatial information regarding a distance between the branch instruction and a target instruction of the branch instruction; a branch predictor to predict whether the branch instruction is to be taken; and a branch target buffer (BTB) coupled to the branch predictor. The BTB, based at least in part on the spatial information, may allocate an entry for the branch instruction in one of a first portion of the BTB and a second portion of the BTB. Other embodiments are described and claimed.

Techniques for permuting two source two dimensional (2D) arrays are described. A processor of an aspect includes a decoder circuitry to decode an instruction having an opcode. The instruction may indicate a first source 2D array, a second source 2D array, and permute control elements. Execution circuitry is coupled with the decoder circuitry. The execution circuitry is to execute the decoded instruction to select data elements, from among any data elements of the first source 2D array, and any data elements of the second source 2D array, that are each indicated by a different corresponding one of the permute control elements. The execution circuitry is also to store the selected data elements in data element positions of a result 2D array that each correspond to a different one of the permute control elements. Other processors, methods, systems, and instructions are disclosed.

Techniques and mechanisms to efficiently provide features of a secure authentication mode (SEAM) by a processor. In an embodiment, cores of the processor support an instruction set which comprises instructions to invoke the SEAM. One such core installs an authenticated code module (ACM), which is executed to load a persistent SEAM loader module (P-SEAMLDR) in a reserved region of a system memory. In turn, the P-SEAMLDR loads into the reserved region a SEAM module which facilitates trust domain extension (TDX) protections for a given trusted domain. In another embodiment, the instruction set supports a SEAM call instruction with which either of the P-SEAMLDR or the SEAM module is accessed in the reserved region.

In an embodiment, a processor includes: a fetch circuit to fetch instructions, the instructions including a sum of squared differences (SSD) instruction; a decode circuit to decode the SSD instruction; and an execution circuit to, during an execution of the decoded SSD instruction, generate an SSD output vector based on a plurality of input vectors, the SSD output vector including a plurality of squared differences values. Other embodiments are described and claimed.

In an embodiment, a processor includes a fetch circuit to fetch instructions, the instructions including a code prefetch instruction; a decode circuit to decode the code prefetch instruction and provide the decoded code prefetch instruction to a memory circuit, the memory circuit to execute the decoded code prefetch instruction to prefetch a first set of code blocks into a first cache and to prefetch a second set of code blocks into a second cache. Other embodiments are described and claimed.

Techniques for extracting strided data elements from three source two dimensional (2D) arrays are described. A processor of an aspect includes a decoder circuitry to decode an instruction having an opcode. The instruction may indicate a first source 2D array, a second source 2D array, and a third source 2D array. Execution circuitry is coupled with the decoder circuitry. The execution circuitry is to execute the decoded instruction to select, for each one dimensional (1D) array of data elements in a first dimension, of each of the first, second, and third source 2D arrays, only a plurality of data elements at data element positions separated by a stride of three. The execution circuitry is also to store the selected plurality of data elements in a result 2D array in a destination storage location. Other processors, methods, systems, and instructions are disclosed.

Aspects include circuitry that includes a first global generation counter (GGC) that is increased upon decoding of a branch instruction and a second GGC that is increased upon a completion of the branch instruction. Upon a triggered rollback, the first GGC is reset. The circuitry also includes a generation tag memory associated with a register that receives loads during a side-channel attacks which is set to the first GGC upon a first load, and a determination unit to determine, for a second load from an address depending on the register of the first load, a generation tag value associated with the register of the second load as a function of the first GGC, the second GGC, and the generation tag value associated with the register of the first load. A wait queue is configured to block the second load, if the generation tag is larger than the second GGC.

A computer system, processor, computer program product, and method for executing instructions in a software application that includes a processor that can be dynamically controlled, in response to a value set in a control register, to operate in either a secure mode or a performance mode. In the secure mode, the processor: upon encountering a secure mode entry instruction, computes an entry hash value using a hash function and stores the entry hash value; and upon encountering a secure mode exit instruction, computes an exit hash value, loads the entry hash value, and determines whether the entry hash value is the same as the exit hash value, and depending upon verification of the hash values can execute the return function or transfer control to the operating system. In the performance mode, the processor: executes both the secure mode entry instruction and the secure mode exit instruction as no-operations.

A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.