A predicated vector load micro-operation specifies a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive. A predetermined type of predicated vector load micro-operation can be issued to the processing circuitry before the predicate operand is determined to meet an availability condition, and if issued in this way memory access circuitry can determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition, and if the predetermined condition is unsatisfied, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register.

A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.

An arithmetic processing device that executes a single instruction/multiple data (SIMD) operation, includes a memory; and a processor coupled to the memory and configured to register an indefinite cycle instruction of a plurality of instructions to a first queue, register other instructions other than the indefinite cycle instruction of the plurality of instructions to a second queue, issue the indefinite cycle instruction registered to the first queue, and issue the other instructions registered to the second queue after issuing the indefinite cycle instruction.

Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for using a virtual desktop. A method in one embodiment includes receiving, at a first edge node in a plurality of edge nodes, an instruction from a first set of input devices in a plurality of peripheral devices. The instruction is for use of a first virtual desktop deployed on the first edge node. The method further includes: using the first virtual desktop based on the instruction by using resources at the first edge node. The method further includes: sending data to an output device in the plurality of peripheral devices, wherein the data is associated with the use of the first virtual desktop. The solution for using a virtual desktop of the present application enables the use of a virtual desktop using resources at an edge node without requiring a client.

A task optimization method and a task optimization device in a mobile robot are provided. The task optimization method includes: obtaining at least one task type in a mobile robot and usage information when all users use a task corresponding to each task type; separately performing machine learning on the usage information of all the users corresponding to each task type to obtain at least one piece of user's usage habit information corresponding to each task type and usage probability thereof, thereby performing machine learning on usage information when all users use the task corresponding to the task type; based on the at least one piece of usage habit information corresponding to each task type, the usage probability thereof and the real-time usage information, optimizing the task corresponding to the task type used by the user in real time.

A system for allocation of resources and processing jobs within a distributed system includes a processor and a memory coupled to the processor. The memory includes at least one process and at least one resource allocator. The process is adapted for processing jobs within a distributed system which receives jobs to be processed. The resource allocator is communicably coupled with at least one process, and is adapted to generate one or more sub-processes within a limit of one or more resources allocated to the process for processing jobs.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

Stateful microbranch instructions, including: generating, based on an instruction, a first one or more microinstructions including a stateful microbranch instruction, wherein the stateful microbranch instruction includes: an address of a next instruction after the instruction; a branch target address; one or more microcode attributes; and executing the first one or more microinstructions.

A method for automated machine learning includes controlling execution of a plurality of instantiations of different automated machine learning frameworks on a machine learning task each as a separate arm in consideration of available computational resources and time budget. During the execution by the separate arms, a plurality of machine learning models are trained and performance scores of the plurality of trained machine learning models are computed such that one or more of the plurality of trained machine learning models are selectable for the machine learning task based on the performance scores. This invention can be used for predicting patient discharge, predictive control in buildings for energy optimization, and so on.

A method of increasing computer hardware efficiency of a matrix computation. The method comprises receiving at a computer processing device, digital signals encoding one or more operations of the matrix computation, each operation including one or more operands. The method further comprises, responsive to determining, by a sparse data check device of the computer processing machine, that an operation of the matrix computation includes all dense operands, forwarding the operation to a dense computation device of the computer processing machine configured to perform the operation of the matrix computation based on the dense operands. The method further comprises, responsive to determining, by the sparse data check device, that an operation of the matrix computation includes one or more sparse operands, forwarding the operation to a sparse computation device configured to perform the operation of the matrix computation.