A system performs continuous delivery of a data pipeline on a cloud platform. The system receives a specification of the data pipeline that is split into smaller specifications of data pipeline units. The system identifies a target cloud platform and generates a deployment package for each data pipeline unit for the target cloud platform. The system creates a connection with the target cloud platform and uses the connection to provision computing infrastructure on the target cloud platform for the data pipeline unit according to the system configuration of the data pipeline unit. The data pipeline may be implemented as a data mesh that is a directed acyclic graph of nodes, each node representing a data pipeline unit. Different portions of the data mesh may be modified independent of each other. Partial results stored in different portions of the data mesh may be recomputed starting from different points in time.

A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

Aspects of the present disclosure relate to an apparatus. Instruction information generation circuitry generates instruction information. Instruction information storage circuitry comprises a plurality of elements having physical sub-elements configured to temporarily store units of instruction information, Allocation circuitry is configured to receive, from the instruction information generation circuitry, given instruction information, It determines a mapping of a plurality of ordered virtual sub-elements, such that each virtual sub-element maps onto a respective one of said physical sub-elements. The given instruction information is stored into the virtual sub-elements of a given element, according to the mapping, such that at least one virtual sub-element lower in said order has a higher priority than at least one virtual sub-element higher in said order. Sub-element deactivation circuitry is configured to track usage of said virtual sub-elements across the plurality of elements and adaptively deactivate virtual sub-elements.

An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.

Methods, systems, and devices for pipeline fusion of a plurality of kernels. In some implementations, a first batch of a first kernel is executed on a first processing device to generate a first output of the first kernel based on an input. A first batch of a second kernel is executed on a second processing device to generate a first output of the second kernel based on the first output of the first kernel. A second batch of the first kernel is executed on the first processing device to generate a second output of the first kernel based on the input. The execution of the second batch of the first kernel overlaps at least partially in time with executing the first batch of the second kernel.

Methods and systems for distributing instructions amongst processing units in a processing pipeline are disclosed. A method includes compiling a set of instructions for a stage of a multistage programmable processing pipeline in which the stage of the multistage programmable processing pipeline includes multiple processing units configured to processes instructions in parallel, wherein compiling the set of instructions includes, identifying first and second subsets of instructions within the set of instructions that can be executed independent of each other, assigning the first subset of instructions to a first processing unit of the stage, assigning the second subset of instructions to a second processing unit of the stage, and executing the first and second subsets of instructions in parallel at the first and second processing units, respectively.

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.