The present invention discloses an electronic apparatus operation method having elastic boot file allocation mechanism that includes steps outlined below. A system activation procedure is executed by a processing circuit to load a hard code setting data from a boot code block of a boot data storage circuit to a system storage circuit. Version setting data is loaded to the system storage circuit to replace at least a part of the hard code setting data to generate boot setting data by the processing circuit when the version setting block is determined to include the version setting data by the processing circuit. The system activation procedure is proceeded to be executed according to the boot setting data by the processing circuit.

In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

An information handling system may include a plurality of information handling resources comprising firmware elements; at least one processor; and a computer-readable medium having instructions thereon that are executable by the at least one processor for: storing metadata associated with data that is stored in the plurality of firmware elements of the information handling system; and implementing a single filesystem configured to allow unified access to the data via the metadata.

Disclosed herein are network elements for use in a transport network and methods of using the same. The network elements may comprise an embedded device having a processor, a communication device in communication with the processor, a first memory, a second memory, and a third memory. The third memory may store a hybrid boot sequence comprising computer-executable instructions that when executed by the processor of the embedded device cause the embedded device to: determine whether a first kernel image is stored on the first memory; responsive to the determination that the first kernel image is not stored on the first memory, obtain a second kernel image stored on a remote network element; store at least one of the first kernel image and the second kernel image on the second memory as a primary kernel image; and boot the primary kernel image stored on the second memory.

An electronic apparatus includes: a memory; a storage configured to store a first operating system; and a processor configured to: perform booting by loading the first operating system stored in the storage to the memory, and store data, obtained based on the first operating system running, in the storage, load an obtained second operating system and the data stored in the storage to the memory, identify operation compatibility between the second operating system and the data loaded to the memory, perform booting by loading the second operating system to the memory, based on identification of normal operation compatibility, and perform booting by loading the first operating system to the memory, based on identification of abnormal operation compatibility.

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

A self-optimizing System-on-Chip (SOC) includes multiple cores, multiple hardware accelerators, multiple memories and an interconnect framework. The SOC also includes a machine learning (ML) module that uses data flow information to build a ML network dynamically and configures all the various hardware blocks autonomously, to achieve predetermined application performance targets. The SOC is able to recover from hangs caused when testing various configuration settings. The SOC also avoids configuration settings that cause severe drops in performance.

Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.

A server and an updating method for a MAC address are provided in the present application. The server includes: a network chipset having a preset first MAC address; a first non-volatile memory storing the first MAC address of the network chipset; a second non-volatile memory storing a first BIOS code data; a central processing unit coupled to the network chipset and the second non-volatile memory; and a baseboard management controller coupled to the central processing unit, the first non-volatile memory, and the second non-volatile memory. The baseboard management controller reads the first non-volatile memory to obtain the first MAC address and stores a second BIOS code data including the first MAC address to the second non-volatile memory, causing the first BIOS code data to be overwritten by the second BIOS code data