A basic input/output system provides an interface for a core aggregation layout that identifies a grouping of processor cores into core aggregations, wherein each of the core aggregations is associated with a maximum allowable C-state. A processor may monitor an information handling system during operation of an application to gather data associated with latency sensitivity of the application, update the core aggregation layout based on the data gathered during the operation of the application, and pin a thread for execution to one of the processor cores based on the latency sensitivity of the application and the maximum allowable C-state.

Embodiments of this disclosure are directed towards a method of logging messages in a baseboard management controller (BMC) system. The method includes powering on a processing chip of the BMC system, wherein the processing chip has a main processor and a co-processor that is communicatively coupled to a non-transitory processor-readable memory device and snooping interface. The method further includes booting up the co-processor, and initiating a storage portion of the non-transitory processor-readable memory device the snooping interface. The method further includes triggering a boot-up of the main processor, and receiving, via the snooping interface, the messages redirected from a communication interface of the BMC system.

This application provides a kernel reboot method, to reserve an internal memory for storing an entry address of a physical code and a code segment for the physical core. A kernel hotswap scenario is used as an example. When a computer system stops executing an old kernel, an interrupt is sent to the physical core, so that the physical core enters a busy waiting state. When the computer system starts a new kernel, the entry address of the physical core is modified. When finding that the entry address is modified, the physical core in the busy waiting state exits the busy waiting state, performs an initialization procedure of the physical core, and receives task scheduling of the new kernel.

Systems and methods are described for communications across privilege domains within a central processing unit (“CPU”) core. The CPU core can store a kernel context associated with an operating system within the CPU. An application can request access to the CPU, and the CPU can load a user context associated with the application into the CPU. The CPU can execute instructions from the application while both the kernel context and the user context persist in the CPU. Because both contexts are stored on the CPU, the CPU can switch contexts without loading or unloading context data from memory.

Systems and methods are disclosed including a method comprising sending, by a monitored central processing unit (CPU) to a monitoring CPU of a memory sub-system controller, an address range of a logging data structure stored within a local memory component of the monitored CPU; storing, in the logging data structure by the monitored CPU, a log file comprising system state information associated with one or more tasks performed by the monitored CPU; executing, by the monitoring CPU, a data-gathering task to retrieve the log file from the logging data structure; and sending, by the monitoring CPU, the log file to a host system.

A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.

A processor includes at least one socket and at least one memory. Each socket includes a first die and a second die. The first die receives a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputs a boot-completion signal after completing the boot procedure. The second die receives the internal boot-enable signal and the boot-completion signal from the first die to execute the boot procedure. The second die is electrically connected to the first die through a communication bus. The memory is electrically connected to the second die. When the first die executes the boot procedure, the first die accesses the memory through the communication bus and the second die.

Described embodiments provide systems and methods for determining bounce-able machines. One or more processors can be coupled to memory. The one or more processors can identify data associated with a history of actions performed on a plurality of machines. The one or more processors can determine, using the data, a change in performance of the plurality of machines if a sequence of actions were applied to one or more of the plurality of machines. The one or more processors can select a machine of the plurality of machines based on at least on the change in performance of the machine satisfying a threshold. The one or more processors can initiate, responsive to the selection, the sequence of actions on the machine.

Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.

In an embodiment, a system includes a contactless reader and an apparatus. The apparatus includes a contactless transponder including a contactless interface and a transponder wired interface and being configured to communicate with a contactless reader according to a contactless protocol through the contactless interface. The apparatus includes a bus coupled to the transponder wired interface, and at least one module coupled to the bus, the at least one module including a processing circuit, the contactless reader being configured to communicate instructions of a software program executable by the processing circuit to the at least one module through the contactless transponder.