Disclosed herein are system, method, and computer program product embodiments for multi-cluster boot-strapping. In some embodiments, a server residing on a primary computing cluster receives a first request to establish a temporary connection between the primary computing cluster and a secondary computing cluster. The server establishes the temporary connection between the primary computing cluster and the secondary computing cluster using the first set of credentials. Furthermore, the server receives a second request to establish a persistent connection between the primary computing cluster and the secondary computing cluster. The server establishes the persistent connection by transmitting a third request comprising the configuration settings to the secondary computing cluster thereby causing the secondary computing cluster to generate a second set of credentials corresponding to the primary computing cluster. The server receives and stores the second set of credentials.

A basic input/output system (BIOS) may load an embedded operating system (EOS), and the light-weight EOS may operate as a single captive portal for all pre-boot operations. With a single captive portal, the EOS may provide a multi-task environment to facilitate quicker execution of multiple pre-boot tasks within a single environment to reduce a number of reboots. In some embodiments, power consumption by performing the tasks within the EOS may be reduced by executing operations using a low-power core of an information handling system, such as a “little” core of a system on chip (SoC) having multiple “big” and “little” cores or a hybrid core of an information handling system. More generically, the EOS may execute on one or both of a first processor core and second processor core of an information handling system, in which the first and second processor cores are configured differently.

In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.

Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.

A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes at least one or more processors and on-chip memory. The on-chip memory has a higher security level than off-chip memory. One of the one or more processors is designated as a security processor. During the processing of the multiple boot steps of a bootup operation, the security processor initializes a message queue in on-chip memory. The security processor also loads multiple modules from off-chip memory into the on-chip memory. The processor executes the multiple loaded modules in an order based on using the message queue to implement inter-module communication among the plurality of boot modules. The security processor transfers requested data between modules using messages from the modules and data storage of the message queue. The modules are completed without reloading any modules from off-chip memory.

An example method of initializing a plurality of processors in a hardware platform of computing device for use by system software executing on the hardware platform includes: parsing a descriptor table that has been loaded into memory from firmware to identify an original boot protocol for initializing at least one secondary processor of the plurality of processors; creating at least one mailbox structure in the memory associated with the at least one secondary processor; causing the at least one secondary processor to execute secondary processor initialization code stored in the memory, the secondary processor initialization code implementing a mailbox-based boot protocol that uses the at least one mailbox structure to initialize the at least one secondary processor; and modifying the descriptor table to identify the mailbox-based boot protocol for initializing the at least one secondary processor in place of the original boot protocol.

The present invention provides a vehicle control device with which, even when an abnormality is detected in a core in a multi-core processor, it is possible to reduce the time needed until the core in which the abnormality is detected restarts and re-executes application software. The present invention is characterized by being provided with: a diagnostic means for carrying out a diagnostic process when starting a processor core, the diagnostic process including hardware diagnosis performed by hardware and software diagnosis performed using software after the hardware diagnosis; and a diagnostic process information change processing means for changing the method for executing the diagnostic process when all of the processor cores are started and when one of the processor cores is restarted.

At power on of a computing device, a baseboard management controller (BMC) of the computing device executes, a first-stage bootloader program to download a second-stage bootloader program from a first server. The BMC executes the second-stage bootloader program to download third-stage firmware of the BMC from a second server. The BMC executes the third-stage firmware to download firmware of a primary processing subsystem of the computing device from a third server, and to start the primary processing subsystem by causing the primary processing subsystem to execute the firmware of the primary processing subsystem.

An apparatus is described. The apparatus includes a plurality of processing cores and at least one accelerator within a semiconductor chip package. The accelerator is to offload at least one task from the processing cores after boot-up of the processing cores and the accelerator. The accelerator is also to perform authentication of firmware during the boot-up. The firmware is to execute on one of the at least one accelerator.

An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.