Patent classifications
G06F9/4411
Application profiling for power-performance management
A processing apparatus is provided which includes memory configured to store hardware parameter settings for each of a plurality of applications. The processing apparatus also includes a processor in communication with the memory configured to store, in the memory, the hardware parameter settings, identify one of the plurality of applications as a currently executing application and control an operation of hardware by tuning a plurality of hardware parameters according to the stored hardware parameter settings for the identified application.
Docking station, electrical device, and method for configuring basic input output system
A docking station includes a network interface controller (NIC), a dock-side controller and a dock-side connector interface. The NIC is configured to transmit one or more management component transport protocol (MCTP) packets via a system management bus (SMbus). The dock-side controller is electrically coupled to the SMbus, and configured to encode the one or more MCTP packets to one or more vendor specific protocol (VSP) packets. The dock-side connector interface is electrically coupled to the dock-side controller, and configured to transmit the one or more VSP packets to an electrical device to control a basic input output system (BIOS) of the electrical device on the condition that the electrical device is connected to the docking station via the dock-side connector interface.
Runtime device firmware verification using trust chaining
Systems and methods are disclosed herein that may implement an information handling system including a gateway and a peripheral device monitor. The gateway may interface peripheral devices and control access of host resources of the information handling system by any of the peripheral devices. The peripheral device monitor may detect connection of an unverified peripheral device to the gateway, perform a trust verification process with the unverified peripheral device, control the gateway to enable access of the host resources by the unverified peripheral device when the unverified peripheral device becomes verified, and control the gateway to prevent access to the host resources by the unverified peripheral device when the unverified peripheral device fails the trust verification process. The trust verification process may include validating a device certificate and verifying a digest of boot code of the peripheral device. The peripheral device monitor may perform a verification failure procedure when the unverified peripheral device fails the trust verification process.
Split protocol approaches for enabling devices with enhanced persistent memory region access
A host command is received to configure a system to have a configuration designating a first interface standard at a first port for exposing a storage element and a second interface standard at a second port for exposing a persistent memory region (PMR). The storage element is implemented on a first memory device of the system and the PMR is implemented on a second memory device of the system. The second interface standard implements one or more alternate protocols supported by the first interface standard. The system is configured in accordance with the configuration.
Datapath load distribution for a RIC
To provide a low latency near RT RIC, some embodiments separate the RIC's functions into several different components that operate on different machines (e.g., execute on VMs or Pods) operating on the same host computer or different host computers. Some embodiments also provide high speed interfaces between these machines. Some or all of these interfaces operate in non-blocking, lockless manner in order to ensure that critical near RT RIC operations (e.g., datapath processes) are not delayed due to multiple requests causing one or more components to stall. In addition, each of these RIC components also has an internal architecture that is designed to operate in a non-blocking manner so that no one process of a component can block the operation of another process of the component. All of these low latency features allow the near RT RIC to serve as a high speed IO between the E2 nodes and the xApps.
VIRTUAL MACHINE MIGRATION METHOD AND RELATED DEVICE
Embodiments of this application disclose a virtual machine migration method. One example method includes: indicating, by a controller, a proxy virtual machine to mount a volume; replacing, by using the proxy virtual machine, a driver of an original platform in the volume with a driver of a target platform; and then, mounting a replaced volume to a target virtual machine.
RUNTIME CONFIGURATION OF CHIPSET TO SUPPORT MULTIPLE I/O SUBSYSTEM VERSIONS WITH ONE BIOS IMAGE
A method for configuring a peripheral bus of an information handling system performs, as part of a boot sequence, an initial configuration of a chipset setting pertaining to the bus based on a descriptor stored in a nonvolatile storage resource. After an operating system is loaded, a controller detects a peripheral device connecting to the bus and responds by performing a runtime configuration of the chipset setting based on capability information obtained from the peripheral device. The peripheral bus may comprise a USB pipe and a USB-C type connector, wherein the peripheral device is detected by a USB power delivery (PD) controller based on configuration channel (CC) pins of the USB-C connector. The PD controller may signal the chipset and send the device's capability information to the chipset. The PD controller may assert a PMCALERT# signal of the chipset's and send the capability information via a system management link (SMLink1) .
DRIVER INSTALLATION GUIDING CONTROL METHOD, DEVICE REGARDING THE SAME, AND TERMINAL
A driver installation guiding control method includes: obtaining a detection result of whether a terminal is equipped with a Bluetooth module; and according to the detection result, determining a driver installation guiding control user interface to be displayed.
Storage enclosures
In one example, a physical storage enclosure can include a storage area to enclose a device, a locking mechanism to prevent removal of the device from the storage area, a logical configuration system coupled to the device within the storage area, wherein the logical configuration system includes instructions to identify the device within the storage area and alter instructions associated with the device within the storage area, a hardware logistic system coupled to the locking mechanism to activate and deactivate the locking mechanism, and a firewall to restrict communication between the logical configuration system and the hardware logistic system.
CONFIGURABLE COMPUTER MEMORY
A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.