G06F9/44589

SYSTEM AND METHOD FOR DATA-LAYOUT AWARE DECOMPRESSION AND VERIFICATION USING A HARDWARE ACCELERATOR CHAIN
20220309030 · 2022-09-29 ·

A computer implemented method of data decompression and verification includes decompressing a compressed data segment to generate a decompressed data region. The method also includes generating a segment vector array (SVA) including a number of segment vectors corresponding to data segments within the decompressed data region, each segment vector indicating a location and a size of a corresponding data segment. The method also includes transmitting the SVA to a chain plugin module and transmitting segment vector array data to a SVA-based message constructor. The method also includes constructing a SVA-based message including the location and size of data segments within the decompressed data region, and transmitting the SVA-based message to a hardware accelerator. The method also includes performing verification sessions at the hardware accelerator, each verification session corresponding to a specific data segment indicated by the SVA-based message.

EXECUTION CODE PROVISION METHOD AND SOFTWARE DEVELOPMENT SYSTEM
20220269773 · 2022-08-25 · ·

A solution can ensure the security of an application program. An execution code provision method includes: a step of generating a source code according to a user operation; a step of generating an intermediate representation from the source code; a step of verifying whether or not the intermediate representation satisfies a predetermined rule or regulation; and a step of realizing execution of an execution code generated from the intermediate representation when the intermediate representation satisfies the predetermined rule or regulation.

Simulating black box test results using information from white box testing

Systems, methods are program products for simulating black box test results using information obtained from white box testing, including analyzing computer software (e.g., an application) to identify a potential vulnerability within the computer software application and a plurality of milestones associated with the potential vulnerability, where each of the milestones indicates a location within the computer software application, tracing a path from a first one of the milestones to an entry point into the computer software application, identifying an input to the entry point that would result in a control flow from the entry point and through each of the milestones, describing the potential vulnerability in a description indicating the entry point and the input, and presenting the description via a computer-controlled output medium.

DATA STRUCTURE ABSTRACTION FOR MODEL CHECKING

This disclosure relates generally to data structure abstraction, and more particularly to method and system for data structure abstraction for model checking. In one embodiment, the method includes identifying data structure accesses in the source code. Loops are identified in the data structure accesses, and loop-types are identified in the loops. An abstracted code is generated based on the loop types for abstracting the data structure. Abstracting the data structure includes, for each loop, replacing the data structure accesses by one of a corresponding representative element and a non-deterministic value in the loop body of said loop based on elements accessed, and eliminating loop control statement of said loop operating on elements of data structure based on loop type of said loop, and adding a plurality of non-array assignments at a start and after the loop body of the source code. The abstracted code is provided for the model checking.

CODE TESTING METHOD, APPARATUS AND DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM

The invention discloses a code testing method. The method includes the following steps of: acquiring a code set to be tested; loading the code set to a corresponding operating chip, and executing the code set by using the operating chip; judging whether a target code subset which is not successfully executed exists in the code set; and if yes, performing an audit testing operation on the code set. The code testing method provided by the invention is simple and feasible to apply, which improves a testing reliability and reduces a testing cost. The invention also discloses a code testing apparatus and device, and a storage medium, which have corresponding technical effects.

NATIVE-IMAGE IN-MEMORY CACHE FOR CONTAINERIZED AHEAD-OF-TIME APPLICATIONS
20220197682 · 2022-06-23 ·

A method includes identifying an ahead-of-time (AOT) native-image application to be compiled and during AOT compilation of the AOT native-image application; bypassing an operating system page cache corresponding to the AOT native-image application; and accessing, by a processing device, the native-image application from an in-memory cache shared using inter-process-communication.

Methods, blockchain nodes, and node devices for executing smart contract

Computer-implemented methods, non-transitory, computer-readable media, and computer-implemented systems are provided for executing a smart contract in a blockchain network. The computer-implemented method includes: compiling, by a blockchain node in a blockchain network, code of a smart contract into machine code through Just-In-Time (JIT) compilation after deploying the smart contract, wherein the code of the smart contract comprises hotspot code marked by a hotspot identifier; storing, by the blockchain node, the hotspot code marked by the hotspot identifier; and when executing the smart contract, in response to determining that the machine code corresponding to the code of the smart contract is locally stored, executing, by the blockchain node, the machine code.

DEVICES, SYSTEMS, AND METHODS FOR PROVIDING ON-DEMAND ENGINE SOFTWARE USING A DISTRIBUTED LEDGER
20220179630 · 2022-06-09 · ·

Devices, systems, and methods for providing software to aircraft using a distributed ledger are disclosed. A software delivery system includes aircraft having an engine control system configured to verify and install software utilized by components of the aircraft, an electronic distribution system coupled to the aircraft, an edge manager coupled to the electronic distribution system, and computing devices acting as nodes in a distributed ledger base maintaining a distributed ledger. The electronic distribution system verifies a request for software, requests software, and initiates an installation protocol with the engine control system. The edge manager maintains software. The distributed ledger base is coupled to the aircraft, the electronic distribution system, and the edge manager. The distributed ledger provides a record including information pertaining to a request for software, verifications of the request by the electronic distribution system, the edge manager, and the engine control system, and an installation of the software.

VEHICLE CONTROL DEVICE, VEHICLE CONTROL METHOD, AND RECORDING MEDIUM RECORDING CONTROL PROGRAM

A vehicle control device includes a re-use determination section and a verification section. When the software of a virtual machine is to be verified, the re-use determination section decides, in accordance with an index assigned beforehand to the virtual machine, whether or not to re-use a verification result of common software that has been obtained in verification of the software of another virtual machine. When the re-use determination section decides to re-use the verification result of the common software obtained in the verification of the software of the other virtual machine, the verification section re-uses the verification result of the common software obtained in the verification of the software of the other virtual machine and verifies VM software of the virtual machine.

Calculation processing apparatus, and method for controlling calculation processing apparatus
11355212 · 2022-06-07 · ·

An offset address generator generates a plurality of offset addresses at an interval of a basic processing unit size on the basis of an access destination address from a calculating circuit, partitions an access destination memory region from the calculating circuit to set a plurality of verification address ranges. A determiner sequentially determines whether the plurality of set verification address ranges are matched with a monitoring target address. With this configuration, it is possible to simplify the configuration of a debug function in a processor.