Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.

In one embodiment, a software agent profiler process attaches to an application and a primary instrumentation interface for the application, and discovers one or more software agents associated with the application. The software agent profiler process may then launch the one or more software agents within an encapsulated container environment of the software agent profiler process by configuring each of the one or more software agents, respectively, to point to a proxy instrumentation interface of the software agent profiler process instead of the primary instrumentation interface for the application. As such, the software agent profiler process may receive calls from the one or more software agents on the proxy instrumentation interface of the software agent profiler process, and can manage the calls from the one or more application agents prior to the calls being passed to the primary instrumentation interface for the application.

A computationally implemented system and method that is designed to, but is not limited to: electronically processing mobile operating system object code at least partially from mobile device storage to direct to one or more origination mobile communication device display surfaces an origination mobile communication device user interface presentation of communication characteristics information regarding one or more mobile operating system based communication devices for operation as one or more ad hoc intermediary relays of one or more fallback communication networks upon initiation thereof for communication between an origination mobile communication device and a destination electronic communication device. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure.

A computer architecture providing enhanced JVM security and a method of providing enhanced security for a JVM are disclosed. The host computer runs a single, first, trusted JAVA API library above which is located a hypervisor software layer, and then at least one untrusted JAVA API library. The code of each second, upper, untrusted JAVA API library is modified at, or before runtime to call the hypervisor software layer instead of the JVM to thereby create a silo corresponding to each of the second, upper, untrusted JAVA API libraries. Each silo extends between the host computer and the corresponding second, upper, untrusted JAVA API library. The hypervisor software layer is operated to only permit communication between each of the second, upper, untrusted JAVA API libraries and a corresponding portion of the memory and functional assets of the host computer. Consequently, each of the second, upper, untrusted JAVA API libraries cannot communicate with all of the host computer memory and/or all of the host computer functional assets. A computer program product is also disclosed.

The present invention provides a method of implementing an ARM64-bit floating point emulator on a Linux system, which includes: running an ARM64-bit instruction on the Linux system; applying an instruction classifier to a first feature code of a machine code indicated by the ARM64-bit instruction to determine whether the ARM64-bit instruction is an ARM64-bit floating point instruction; and, if the ARM64-bit instruction is an ARM64-bit floating point instruction, applying the instruction classifier to a second feature code of the machine code indicated by the ARM64-bit instruction to determine the ARM64-bit floating instruction to be a specific ARM64-bit floating instruction.

A system for an agnostic runtime architecture. The system includes a close to bare metal JIT conversion layer, a runtime native instruction assembly component included within the conversion layer for receiving instructions from a guest virtual machine, and a runtime native instruction sequence formation component included within the conversion layer for receiving instructions from native code. The system further includes a dynamic sequence block-based instruction mapping component included within the conversion layer for code cache allocation and metadata creation, and is coupled to receive inputs from the runtime native instruction assembly component and the runtime native instruction sequence formation component, and wherein the dynamic sequence block-based instruction mapping component receives resulting processed instructions from the runtime native instruction assembly component and the runtime native instruction sequence formation component and allocates the resulting processed instructions to a processor for execution.

A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.

Multi-byte compressed string representation embodiments define a String class control field identifying compression as enabled/disabled, and another control field, identifying a decompressed string created when compression enabled. On pattern matching by a compiler, noping tests based on null setting of stringCompressionFlag and registering a class loading assumption on a nop location. When arguments to a String class constructor are not compressible, a decompressed String is created and stringCompressionFlag initialized. Endian-aware helper methods for reading/writing byte and character values and helper methods for widening, narrowing, truncation, conversion and masking are defined. Enhanced String class constructors, when characters are not compressible, create a decompressed String, and initialize stringCompressionFlag triggering class load assumptions, overwriting all nopable patch points. A String object sign bit is set to one for decompressed strings when compression enabled, and masking/testing this flag bit is noped using stringCompressionFlag and associated class load assumption. Alternative package protected string constructors and operations are provided. Checking a predetermined location to determine whether supplied arguments to a String class constructor are compressible is performed.

A sensor unit includes at least one sensor for detecting and converting measured quantities into sensor signals; at least one microprocessor; at least one memory for program modules for processing sensor signals, the program modules being executable on the microprocessor; and at least one communications interface to an external application processor, the program modules being able to be activated and deactivated via this communications interface, and further program modules are able to be loaded into the memory via this communications interface. The microprocessor includes at least one closed environment for executing plug-in program modules.

A computer-implemented method for generating a secured software application, involves receiving a source software application which has instructions for processing by a process virtual machine. The method involves generating a secured software application comprising a first set of bytecode instructions derived from the source software application, a second set of the bytecode instructions derived from the source software application, and a security component. The first set of bytecode instructions are for processing on a first process virtual machine, in a first process, on a target processing system. The security component comprises instructions which, when executed on the target processing system, will cause the target processing system to provide a second process virtual machine in a second process where it will process instructions from the second set of bytecode instructions.