Patent classifications
G06F9/45533
EXITLESS TIMER ACCESS FOR VIRTUAL MACHINES
A system and method of scheduling timer access includes a first physical processor with a first physical timer executing a first guest virtual machine. A hypervisor determines an interrupt time remaining before an interrupt is scheduled and determines the interrupt time is greater than a threshold time. Responsive to determining that the interrupt time is greater than the threshold time, the hypervisor designates a second physical processor as a control processor with a control timer and sends, to the second physical processor, an interval time, which is a specific time duration. The hypervisor grants, to the first guest virtual machine, access to the first physical timer. The second physical processor detects that the interval time expires. Responsive to detecting that the interval time expired, an inter-processor interrupt is sent from the second physical processor to the first physical processor, triggering the first guest virtual machine to exit to the hypervisor.
OBTAINING OPTICAL SIGNAL HEALTH DATA IN A STORAGE AREA NETWORK
An aspect of obtaining optical signal health data in a SAN includes receiving, by a computer processor, a request for data corresponding to current operational characteristics of elements of a storage area network to which a host system computer has access. A further aspect includes instantiating, by the computer processor, a virtual host bus adapter interface on the host system computer, transmitting, via the virtual host bus adapter interface, the request to the elements in the portion of the storage area network, aggregating data received from each of the elements, and displaying the aggregated data via the computer processor.
Virtualized Multicore Systems With Extended Instruction Heterogeneity
A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.
METHODS AND APPARATUS TO HANDLE DEPENDENCIES ASSOCIATED WITH RESOURCE DEPLOYMENT REQUESTS
An example apparatus includes a dependency graph generator to generate a dependency graph based on a resource request file specifying a first resource and a second resource to deploy to a resource-based service, the dependency graph representative of the first resource being dependent on a second resource, a verification controller to generate a status indicator after a determination that a time-based ordering of a first request relative to a second request satisfies the dependency graph, and a resource controller to cause transmission of the first request and the second request to the resource-based service based on the dependency graph, and, after determining that the time-based ordering of the first request relative to the second request satisfies the dependency graph, cause transmission of the status indicator to a user device.
Database protocol for exchanging forwarding state with hardware switches
Some embodiments provide a set of one or more network controllers that communicates with a wide range of devices, ranging from switches to appliances such as firewalls, load balancers, etc. The set of network controllers communicates with such devices to connect them to its managed virtual networks. The set of network controllers can define each virtual network through software switches and/or software appliances. To extend the control beyond software network elements, some embodiments implement a database server on each dedicated hardware. The set of network controllers accesses the database server to send management data. The hardware then translates the management data to connect to a managed virtual network.
Data management method and apparatus, and server
A data management method includes receiving, by a management server, a first request, determining, based on an identifier of a first user in the first request, whether a shadow tenant bucket associated with the identifier of the first user exists, and if the shadow tenant bucket associated with the identifier of the first user exists, storing, in the shadow tenant bucket associated with the identifier of the first user, an acceleration engine image (AEI) that the first user requests to register, where a shadow tenant bucket is used to store an AEI of a specified user, and each shadow tenant bucket is in a one-to-one correspondence with a user.
Optimized branching using safe static keys
Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location. The processing device may determine whether a value of the safe static key is initialized. Responsive to determining that the value of the safe static key is initialized, the processing device may further replace the branching instruction with an unconditional branching instruction specifying the first target location. Responsive to determining that the value of the safe static key is uninitialized, the processing device may replace the branching instruction with a conditional branching instruction specifying the first target location.
COHERENCE-BASED DYNAMIC CODE REWRITING, TRACING AND CODE COVERAGE
A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.
APPLICATION COMPONENT IDENTIFICATION AND ANALYSIS IN A VIRTUALIZED COMPUTING SYSTEM
An example method of application identification in a virtualized computing system having a cluster of hosts, the hosts including virtualization layers supporting virtual machines (VMs), is described. The method includes: executing, by application analysis software, process discovery agents for the VMs; receiving, at the application analysis software from the process discovery agents, process metadata describing processes executing on the VMs; generating signatures for the processes based on the process metadata; and determining components of an application based on the signatures.
CUSTOM METADATA COLLECTION FOR APPLICATION COMPONENTS IN A VIRTUALIZED COMPUTING SYSTEM
An example method includes: executing, by application analysis software executing in the virtualized computing system, process discovery agents on the VMs; receiving, at the application analysis software from the process discovery agents, process metadata describing processes executing on the VMs; generating signatures for the processes based on the process metadata; determining components of an application based on the signatures; determining components of an application based on the signatures; identifying, for a first component of the components, a component-specific metadata collector; executing, by the application analysis software, the component-specific metadata collector on a first VM of the VMs; and receiving, at the application analysis software from the component-specific metadata collector, custom metadata further describing a first process of the processes associated with the first component.